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usb: optimize g12a & g12b usb phy reset timing.
PD#173329: usb: optimize g12a & g12b usb phy reset timing. Change-Id: Ib1ffe45d418a6ec023d19e888c54d60cac226473 Signed-off-by: Yue Wang <yue.wang@amlogic.com>
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@@ -49,9 +49,24 @@ EXPORT_SYMBOL_GPL(amlogic_new_usbphy_reset_v2);
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int amlogic_new_usbphy_reset_phycfg_v2(struct amlogic_usb_v2 *phy, int cnt)
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{
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if (phy->reset_regs)
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writel((readl(phy->reset_regs) | (1 << (16 + cnt))),
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phy->reset_regs);
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u32 val;
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u32 temp = 0;
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while (cnt--)
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temp = temp | (1 << (16 + cnt));
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/* set usb phy to low power mode */
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val = readl((void __iomem *)
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((unsigned long)phy->reset_regs + (0x21 * 4 - 0x8)));
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writel((val & (~temp)), (void __iomem *)
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((unsigned long)phy->reset_regs + (0x21 * 4 - 0x8)));
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udelay(100);
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val = readl((void __iomem *)
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((unsigned long)phy->reset_regs + (0x21 * 4 - 0x8)));
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writel((val | temp), (void __iomem *)
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((unsigned long)phy->reset_regs + (0x21 * 4 - 0x8)));
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return 0;
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}
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@@ -134,20 +134,23 @@ static int amlogic_new_usb2_init(struct usb_phy *x)
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}
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writel(reg0.d32, u2p_aml_regs.u2p_r_v2[0]);
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}
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udelay(10);
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amlogic_new_usbphy_reset_phycfg_v2(phy, i);
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udelay(50);
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#if 0
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udelay(10);
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amlogic_new_usbphy_reset_phycfg_v2(phy, phy->portnum);
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udelay(50);
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for (i = 0; i < phy->portnum; i++) {
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for (j = 0; j < 2; j++) {
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u2p_aml_regs.u2p_r_v2[j] = (void __iomem *)
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((unsigned long)phy->regs + i*PHY_REGISTER_SIZE
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+ 4 * j);
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}
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/* ID DETECT: usb2_otg_aca_en set to 0 */
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/* usb2_otg_iddet_en set to 1 */
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writel(readl(phy->phy_cfg[i] + 0x54) & (~(1 << 2)),
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(phy->phy_cfg[i] + 0x54));
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if (i == 1) {
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writel((readl(phy->phy_cfg[i] + 0x50) | (1 << 0)),
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(phy->phy_cfg[i] + 0x50));
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}
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#endif
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reg1.d32 = readl(u2p_aml_regs.u2p_r_v2[1]);
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cnt = 0;
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while (reg1.b.phy_rdy != 1) {
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