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phy: rockchip-snps-pcie3: Configuring grf with clk enabled

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Change-Id: I085e1f3ec19a653d1664dd108859522440cc5563
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
This commit is contained in:
Jon Lin
2025-04-28 10:10:42 +08:00
committed by Tao Huang
parent a221bbbd5a
commit 6bfde08139
1 changed files with 13 additions and 4 deletions
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17
drivers/phy/rockchip/phy-rockchip-snps-pcie3.c
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@@ -264,6 +264,10 @@ static int rockchip_p3phy_probe(struct platform_device *pdev)
return -EINVAL;
}
priv->num_clks = devm_clk_bulk_get_all(dev, &priv->clks);
if (priv->num_clks < 1)
return -ENODEV;
priv->phy_grf = syscon_regmap_lookup_by_phandle(np, "rockchip,phy-grf");
if (IS_ERR(priv->phy_grf)) {
dev_err(dev, "failed to find rockchip,phy_grf regmap\n");
@@ -275,6 +279,13 @@ static int rockchip_p3phy_probe(struct platform_device *pdev)
if (IS_ERR(priv->pipe_grf))
dev_info(dev, "failed to find rockchip,pipe_grf regmap\n");
/* Configuring grf with clk enabled. */
ret = clk_bulk_prepare_enable(priv->num_clks, priv->clks);
if (ret) {
pr_err("failed to enable PCIe bulk clks %d\n", ret);
return ret;
}
ret = device_property_read_u32(dev, "rockchip,pcie30-phymode", &val);
if (!ret) {
priv->pcie30_phymode = val;
@@ -294,6 +305,8 @@ static int rockchip_p3phy_probe(struct platform_device *pdev)
(reg << 16) | reg);
};
clk_bulk_disable_unprepare(priv->num_clks, priv->clks);
priv->phy = devm_phy_create(dev, NULL, &rockchip_p3phy_ops);
if (IS_ERR(priv->phy)) {
dev_err(dev, "failed to create combphy\n");
@@ -306,10 +319,6 @@ static int rockchip_p3phy_probe(struct platform_device *pdev)
priv->p30phy = NULL;
}
priv->num_clks = devm_clk_bulk_get_all(dev, &priv->clks);
if (priv->num_clks < 1)
return -ENODEV;
dev_set_drvdata(dev, priv);
phy_set_drvdata(priv->phy, priv);
phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);