ASoC: rockchip: spdif: Add support for format S32_LE

Treat 32 bit sample width as if it was 24 bits using only
the 24 most significant bits.

Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
Change-Id: Ica236069b6f0ccfa8635cd89bf11dc59bc054d8d
This commit is contained in:
Sugar Zhang
2022-09-02 15:58:28 +08:00
parent 6938d9c200
commit 6c7d5bdf7b
2 changed files with 13 additions and 2 deletions

View File

@@ -160,6 +160,11 @@ static int rk_spdif_hw_params(struct snd_pcm_substream *substream,
break;
case SNDRV_PCM_FORMAT_S24_LE:
val |= SPDIF_CFGR_VDW_24;
val |= SPDIF_CFGR_ADJ_RIGHT_J;
break;
case SNDRV_PCM_FORMAT_S32_LE:
val |= SPDIF_CFGR_VDW_24;
val |= SPDIF_CFGR_ADJ_LEFT_J;
break;
default:
return -EINVAL;
@@ -168,7 +173,8 @@ static int rk_spdif_hw_params(struct snd_pcm_substream *substream,
ret = regmap_update_bits(spdif->regmap, SPDIF_CFGR,
SPDIF_CFGR_CLK_DIV_MASK |
SPDIF_CFGR_HALFWORD_ENABLE |
SDPIF_CFGR_VDW_MASK, val);
SDPIF_CFGR_VDW_MASK |
SPDIF_CFGR_ADJ_MASK, val);
return ret;
}
@@ -262,7 +268,8 @@ static struct snd_soc_dai_driver rk_spdif_dai = {
SNDRV_PCM_RATE_192000),
.formats = (SNDRV_PCM_FMTBIT_S16_LE |
SNDRV_PCM_FMTBIT_S20_3LE |
SNDRV_PCM_FMTBIT_S24_LE),
SNDRV_PCM_FMTBIT_S24_LE |
SNDRV_PCM_FMTBIT_S32_LE),
},
.ops = &rk_spdif_dai_ops,
};

View File

@@ -21,6 +21,10 @@
#define SPDIF_CFGR_CSE_EN BIT(6)
#define SPDIF_CFGR_CSE_DIS 0
#define SPDIF_CFGR_ADJ_MASK BIT(3)
#define SPDIF_CFGR_ADJ_LEFT_J BIT(3)
#define SPDIF_CFGR_ADJ_RIGHT_J 0
#define SPDIF_CFGR_HALFWORD_SHIFT 2
#define SPDIF_CFGR_HALFWORD_DISABLE (0 << SPDIF_CFGR_HALFWORD_SHIFT)
#define SPDIF_CFGR_HALFWORD_ENABLE (1 << SPDIF_CFGR_HALFWORD_SHIFT)