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clk: rockchip: px30: add FRAC_MAX_PRATE limit for uart0

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Change-Id: Id4ec1995a8c406a1eb71da05a04699aa869f52b5
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
This commit is contained in:
Elaine Zhang
2018-12-20 15:07:04 +08:00
committed by Tao Huang
parent ea5569ffc7
commit 6fd905892e
1 changed files with 1 additions and 1 deletions
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drivers/clk/rockchip/clk-px30.c
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@@ -951,7 +951,7 @@ static struct rockchip_clk_branch px30_clk_pmu_branches[] __initdata = {
COMPOSITE_FRACMUX(0, "clk_uart0_frac", "clk_uart0_pmu_src", CLK_SET_RATE_PARENT,
PX30_PMU_CLKSEL_CON(5), 0,
PX30_PMU_CLKGATE_CON(1), 2, GFLAGS,
&px30_uart0_pmu_fracmux, 0),
&px30_uart0_pmu_fracmux, PX30_FRAC_MAX_PRATE),
GATE(SCLK_UART0_PMU, "clk_uart0_pmu", "clk_uart0_pmu_mux", CLK_SET_RATE_PARENT,
PX30_PMU_CLKGATE_CON(1), 3, GFLAGS),