vdin: support afbce output for tm2 [1/1]

PD#SWPL-15188 Problem: display is abnormal when config afbc out in dts Solution: correct vdin reorder mux setting Verify: verified by t962x3_ab301 Change-Id: Ic3ebe1bcba84f7e17c8caa3b12649a406906cabe Signed-off-by: zhiwei.yuan <zhiwei.yuan@amlogic.com>
2026-06-10 12:57:06 +09:00 · 2019-10-15 16:49:00 +08:00
parent d5db1061c3
commit 7018e8433c
20 changed files with 178 additions and 57 deletions
--- a/arch/arm/boot/dts/amlogic/tm2_pxp.dts
+++ b/arch/arm/boot/dts/amlogic/tm2_pxp.dts
@@ -448,8 +448,9 @@
 		 *if support 4K2K-YUV422-10bit-wr:3840*2160*3*6 ~= 160M
 		 *if support 4K2K-YUV422-8BIT-WR:3840*2160*2*4 ~= 64M
 		 *if support 1080p-YUV422-8BIT-WR:1920*1080*2*4 ~= 16M
+		 *worst case:(4096*2160*4 + 2M(afbce issue)) *6buf = 214.5M
 		 */
-		cma_size = <200>;
+		cma_size = <215>;
 		interrupts = <0 83 1>;
 		rdma-irq = <2>;
 		clocks = <&clkc CLKID_FCLK_DIV5>,
@@ -467,11 +468,15 @@
 		 */
 		tv_bit_mode = <0x215>;
 		/* afbce_bit_mode: (amlogic frame buff compression encoder)
-		 * 0: normal mode, not use afbce
-		 * 1: use afbce non-mmu mode
-		 * 2: use afbce mmu mode
+		 * bit0 -- enable afbce
+		 * bit1 -- enable afbce compression-lossy
+		 * bit4 -- afbce for 4k
+		 * bit5 -- afbce for 1080p
+		 * bit6 -- afbce for 720p
+		 * bit7 -- afbce for smaller resolution
 		 */
-		afbce_bit_mode = <0>;
+		afbce_bit_mode = <0x31>;
+		/*urgent_en*/
 	};

 	vdin@1 {
@@ -495,6 +500,7 @@
 		 *bit3:support 12bit
 		 */
 		tv_bit_mode = <0x15>;
+		/*urgent_en*/
 	};

 	tvafe {
--- a/arch/arm/boot/dts/amlogic/tm2_t962e2_ab311.dts
+++ b/arch/arm/boot/dts/amlogic/tm2_t962e2_ab311.dts
@@ -552,8 +552,9 @@
 		 *if support 4K2K-YUV422-10bit-wr:3840*2160*3*6 ~= 160M
 		 *if support 4K2K-YUV422-8BIT-WR:3840*2160*2*4 ~= 64M
 		 *if support 1080p-YUV422-8BIT-WR:1920*1080*2*4 ~= 16M
+		 *worst case:(4096*2160*4 + 2M(afbce issue)) *6buf = 214.5M
 		 */
-		cma_size = <200>;
+		cma_size = <215>;
 		interrupts = <0 83 1>;
 		rdma-irq = <2>;
 		clocks = <&clkc CLKID_FCLK_DIV5>,
@@ -578,7 +579,8 @@
 		 * bit6 -- afbce for 720p
 		 * bit7 -- afbce for smaller resolution
 		 */
-		afbce_bit_mode = <0x0>;
+		afbce_bit_mode = <0x31>;
+		/*urgent_en*/
 	};

 	vdin@1 {
@@ -602,6 +604,7 @@
 		 *bit3:support 12bit
 		 */
 		tv_bit_mode = <0x15>;
+		/*urgent_en*/
 	};

 	tvafe {
--- a/arch/arm/boot/dts/amlogic/tm2_t962e2_ab319.dts
+++ b/arch/arm/boot/dts/amlogic/tm2_t962e2_ab319.dts
@@ -575,8 +575,9 @@
 		 *if support 4K2K-YUV422-10bit-wr:3840*2160*3*6 ~= 160M
 		 *if support 4K2K-YUV422-8BIT-WR:3840*2160*2*4 ~= 64M
 		 *if support 1080p-YUV422-8BIT-WR:1920*1080*2*4 ~= 16M
+		 *worst case:(4096*2160*4 + 2M(afbce issue)) *6buf = 214.5M
 		 */
-		cma_size = <200>;
+		cma_size = <215>;
 		interrupts = <0 83 1>;
 		rdma-irq = <2>;
 		clocks = <&clkc CLKID_FCLK_DIV5>,
@@ -601,7 +602,8 @@
 		 * bit6 -- afbce for 720p
 		 * bit7 -- afbce for smaller resolution
 		 */
-		afbce_bit_mode = <0>;
+		afbce_bit_mode = <0x31>;
+		/*urgent_en*/
 	};

 	vdin@1 {
@@ -625,6 +627,7 @@
 		 *bit3:support 12bit
 		 */
 		tv_bit_mode = <0x15>;
+		/*urgent_en*/
 	};

 	tvafe {
--- a/arch/arm/boot/dts/amlogic/tm2_t962x3_ab301.dts
+++ b/arch/arm/boot/dts/amlogic/tm2_t962x3_ab301.dts
@@ -552,8 +552,9 @@
 		 *if support 4K2K-YUV422-10bit-wr:3840*2160*3*6 ~= 160M
 		 *if support 4K2K-YUV422-8BIT-WR:3840*2160*2*4 ~= 64M
 		 *if support 1080p-YUV422-8BIT-WR:1920*1080*2*4 ~= 16M
+		 *worst case:(4096*2160*4 + 2M(afbce issue)) *6buf = 214.5M
 		 */
-		cma_size = <200>;
+		cma_size = <215>;
 		interrupts = <0 83 1>;
 		rdma-irq = <2>;
 		clocks = <&clkc CLKID_FCLK_DIV5>,
@@ -578,7 +579,8 @@
 		 * bit6 -- afbce for 720p
 		 * bit7 -- afbce for smaller resolution
 		 */
-		afbce_bit_mode = <0x0>;
+		afbce_bit_mode = <0x31>;
+		/*urgent_en*/
 	};

 	vdin@1 {
@@ -602,6 +604,7 @@
 		 *bit3:support 12bit
 		 */
 		tv_bit_mode = <0x15>;
+		/*urgent_en*/
 	};

 	tvafe {
--- a/arch/arm/boot/dts/amlogic/tm2_t962x3_ab309.dts
+++ b/arch/arm/boot/dts/amlogic/tm2_t962x3_ab309.dts
@@ -576,8 +576,9 @@
 		 *if support 4K2K-YUV422-10bit-wr:3840*2160*3*6 ~= 160M
 		 *if support 4K2K-YUV422-8BIT-WR:3840*2160*2*4 ~= 64M
 		 *if support 1080p-YUV422-8BIT-WR:1920*1080*2*4 ~= 16M
+		 *worst case:(4096*2160*4 + 2M(afbce issue)) *6buf = 214.5M
 		 */
-		cma_size = <200>;
+		cma_size = <215>;
 		interrupts = <0 83 1>;
 		rdma-irq = <2>;
 		clocks = <&clkc CLKID_FCLK_DIV5>,
@@ -602,7 +603,8 @@
 		 * bit6 -- afbce for 720p
 		 * bit7 -- afbce for smaller resolution
 		 */
-		afbce_bit_mode = <0>;
+		afbce_bit_mode = <0x31>;
+		/*urgent_en*/
 	};

 	vdin@1 {
@@ -626,6 +628,7 @@
 		 *bit3:support 12bit
 		 */
 		tv_bit_mode = <0x15>;
+		/*urgent_en*/
 	};

 	tvafe {
--- a/arch/arm/boot/dts/amlogic/tm2_t962x3_t312.dts
+++ b/arch/arm/boot/dts/amlogic/tm2_t962x3_t312.dts
@@ -558,8 +558,9 @@
 		 *if support 4K2K-YUV422-10bit-wr:3840*2160*3*6 ~= 160M
 		 *if support 4K2K-YUV422-8BIT-WR:3840*2160*2*4 ~= 64M
 		 *if support 1080p-YUV422-8BIT-WR:1920*1080*2*4 ~= 16M
+		 *worst case:(4096*2160*4 + 2M(afbce issue)) *6buf = 214.5M
 		 */
-		cma_size = <200>;
+		cma_size = <215>;
 		interrupts = <0 83 1>;
 		rdma-irq = <2>;
 		clocks = <&clkc CLKID_FCLK_DIV5>,
@@ -584,7 +585,8 @@
 		 * bit6 -- afbce for 720p
 		 * bit7 -- afbce for smaller resolution
 		 */
-		afbce_bit_mode = <0x0>;
+		afbce_bit_mode = <0x31>;
+		/*urgent_en*/
 	};

 	vdin@1 {
@@ -608,6 +610,7 @@
 		 *bit3:support 12bit
 		 */
 		tv_bit_mode = <0x15>;
+		/*urgent_en*/
 	};

 	tvafe {
--- a/arch/arm64/boot/dts/amlogic/tm2_pxp.dts
+++ b/arch/arm64/boot/dts/amlogic/tm2_pxp.dts
@@ -448,8 +448,9 @@
 		 *if support 4K2K-YUV422-10bit-wr:3840*2160*3*6 ~= 160M
 		 *if support 4K2K-YUV422-8BIT-WR:3840*2160*2*4 ~= 64M
 		 *if support 1080p-YUV422-8BIT-WR:1920*1080*2*4 ~= 16M
+		 *worst case:(4096*2160*4 + 2M(afbce issue)) *6buf = 214.5M
 		 */
-		cma_size = <200>;
+		cma_size = <215>;
 		interrupts = <0 83 1>;
 		rdma-irq = <2>;
 		clocks = <&clkc CLKID_FCLK_DIV5>,
@@ -467,11 +468,15 @@
 		 */
 		tv_bit_mode = <0x215>;
 		/* afbce_bit_mode: (amlogic frame buff compression encoder)
-		 * 0: normal mode, not use afbce
-		 * 1: use afbce non-mmu mode
-		 * 2: use afbce mmu mode
+		 * bit0 -- enable afbce
+		 * bit1 -- enable afbce compression-lossy
+		 * bit4 -- afbce for 4k
+		 * bit5 -- afbce for 1080p
+		 * bit6 -- afbce for 720p
+		 * bit7 -- afbce for smaller resolution
 		 */
-		afbce_bit_mode = <0>;
+		afbce_bit_mode = <0x31>;
+		/*urgent_en*/
 	};

 	vdin@1 {
@@ -495,6 +500,7 @@
 		 *bit3:support 12bit
 		 */
 		tv_bit_mode = <0x15>;
+		/*urgent_en*/
 	};

 	tvafe {
--- a/arch/arm64/boot/dts/amlogic/tm2_t962e2_ab311.dts
+++ b/arch/arm64/boot/dts/amlogic/tm2_t962e2_ab311.dts
@@ -548,8 +548,9 @@
 		 *if support 4K2K-YUV422-10bit-wr:3840*2160*3*6 ~= 160M
 		 *if support 4K2K-YUV422-8BIT-WR:3840*2160*2*4 ~= 64M
 		 *if support 1080p-YUV422-8BIT-WR:1920*1080*2*4 ~= 16M
+		 *worst case:(4096*2160*4 + 2M(afbce issue)) *6buf = 214.5M
 		 */
-		cma_size = <200>;
+		cma_size = <215>;
 		interrupts = <0 83 1>;
 		rdma-irq = <2>;
 		clocks = <&clkc CLKID_FCLK_DIV5>,
@@ -574,7 +575,8 @@
 		 * bit6 -- afbce for 720p
 		 * bit7 -- afbce for smaller resolution
 		 */
-		afbce_bit_mode = <0x0>;
+		afbce_bit_mode = <0x31>;
+		/*urgent_en*/
 	};

 	vdin@1 {
@@ -598,6 +600,7 @@
 		 *bit3:support 12bit
 		 */
 		tv_bit_mode = <0x15>;
+		/*urgent_en*/
 	};

 	tvafe {
--- a/arch/arm64/boot/dts/amlogic/tm2_t962e2_ab319.dts
+++ b/arch/arm64/boot/dts/amlogic/tm2_t962e2_ab319.dts
@@ -575,8 +575,9 @@
 		 *if support 4K2K-YUV422-10bit-wr:3840*2160*3*6 ~= 160M
 		 *if support 4K2K-YUV422-8BIT-WR:3840*2160*2*4 ~= 64M
 		 *if support 1080p-YUV422-8BIT-WR:1920*1080*2*4 ~= 16M
+		 *worst case:(4096*2160*4 + 2M(afbce issue)) *6buf = 214.5M
 		 */
-		cma_size = <200>;
+		cma_size = <215>;
 		interrupts = <0 83 1>;
 		rdma-irq = <2>;
 		clocks = <&clkc CLKID_FCLK_DIV5>,
@@ -601,7 +602,8 @@
 		 * bit6 -- afbce for 720p
 		 * bit7 -- afbce for smaller resolution
 		 */
-		afbce_bit_mode = <0>;
+		afbce_bit_mode = <0x31>;
+		/*urgent_en*/
 	};

 	vdin@1 {
@@ -625,6 +627,7 @@
 		 *bit3:support 12bit
 		 */
 		tv_bit_mode = <0x15>;
+		/*urgent_en*/
 	};

 	tvafe {
--- a/arch/arm64/boot/dts/amlogic/tm2_t962x3_ab301.dts
+++ b/arch/arm64/boot/dts/amlogic/tm2_t962x3_ab301.dts
@@ -550,8 +550,9 @@
 		 *if support 4K2K-YUV422-10bit-wr:3840*2160*3*6 ~= 160M
 		 *if support 4K2K-YUV422-8BIT-WR:3840*2160*2*4 ~= 64M
 		 *if support 1080p-YUV422-8BIT-WR:1920*1080*2*4 ~= 16M
+		 *worst case:(4096*2160*4 + 2M(afbce issue)) *6buf = 214.5M
 		 */
-		cma_size = <200>;
+		cma_size = <215>;
 		interrupts = <0 83 1>;
 		rdma-irq = <2>;
 		clocks = <&clkc CLKID_FCLK_DIV5>,
@@ -576,7 +577,8 @@
 		 * bit6 -- afbce for 720p
 		 * bit7 -- afbce for smaller resolution
 		 */
-		afbce_bit_mode = <0x0>;
+		afbce_bit_mode = <0x31>;
+		/*urgent_en*/
 	};

 	vdin@1 {
@@ -600,6 +602,7 @@
 		 *bit3:support 12bit
 		 */
 		tv_bit_mode = <0x15>;
+		/*urgent_en*/
 	};

 	tvafe {
--- a/arch/arm64/boot/dts/amlogic/tm2_t962x3_ab309.dts
+++ b/arch/arm64/boot/dts/amlogic/tm2_t962x3_ab309.dts
@@ -576,8 +576,9 @@
 		 *if support 4K2K-YUV422-10bit-wr:3840*2160*3*6 ~= 160M
 		 *if support 4K2K-YUV422-8BIT-WR:3840*2160*2*4 ~= 64M
 		 *if support 1080p-YUV422-8BIT-WR:1920*1080*2*4 ~= 16M
+		 *worst case:(4096*2160*4 + 2M(afbce issue)) *6buf = 214.5M
 		 */
-		cma_size = <200>;
+		cma_size = <215>;
 		interrupts = <0 83 1>;
 		rdma-irq = <2>;
 		clocks = <&clkc CLKID_FCLK_DIV5>,
@@ -602,7 +603,8 @@
 		 * bit6 -- afbce for 720p
 		 * bit7 -- afbce for smaller resolution
 		 */
-		afbce_bit_mode = <0>;
+		afbce_bit_mode = <0x31>;
+		/*urgent_en*/
 	};

 	vdin@1 {
@@ -626,6 +628,7 @@
 		 *bit3:support 12bit
 		 */
 		tv_bit_mode = <0x15>;
+		/*urgent_en*/
 	};

 	tvafe {
--- a/arch/arm64/boot/dts/amlogic/tm2_t962x3_t312.dts
+++ b/arch/arm64/boot/dts/amlogic/tm2_t962x3_t312.dts
@@ -561,8 +561,9 @@
 		 *if support 4K2K-YUV422-10bit-wr:3840*2160*3*6 ~= 160M
 		 *if support 4K2K-YUV422-8BIT-WR:3840*2160*2*4 ~= 64M
 		 *if support 1080p-YUV422-8BIT-WR:1920*1080*2*4 ~= 16M
+		 *worst case:(4096*2160*4 + 2M(afbce issue)) *6buf = 214.5M
 		 */
-		cma_size = <200>;
+		cma_size = <215>;
 		interrupts = <0 83 1>;
 		rdma-irq = <2>;
 		clocks = <&clkc CLKID_FCLK_DIV5>,
@@ -587,7 +588,8 @@
 		 * bit6 -- afbce for 720p
 		 * bit7 -- afbce for smaller resolution
 		 */
-		afbce_bit_mode = <0x0>;
+		afbce_bit_mode = <0x31>;
+		/*urgent_en*/
 	};

 	vdin@1 {
@@ -611,6 +613,7 @@
 		 *bit3:support 12bit
 		 */
 		tv_bit_mode = <0x15>;
+		/*urgent_en*/
 	};

 	tvafe {
--- a/drivers/amlogic/media/vin/tvin/vdin/vdin_afbce.c
+++ b/drivers/amlogic/media/vin/tvin/vdin/vdin_afbce.c
@@ -122,12 +122,30 @@ void vdin_write_mif_or_afbce(struct vdin_dev_s *devp,
 		return;

 	if (sel == VDIN_OUTPUT_TO_MIF) {
+		if (is_meson_tm2_cpu()) {
+			rdma_write_reg_bits(devp->rdma_handle,
+				VDIN_TOP_DOUBLE_CTRL, WR_SEL_VDIN0_NOR,
+				MIF0_OUT_SEL_BIT, VDIN_REORDER_SEL_WID);
+			rdma_write_reg_bits(devp->rdma_handle,
+				VDIN_TOP_DOUBLE_CTRL, WR_SEL_DIS,
+				AFBCE_OUT_SEL_BIT, VDIN_REORDER_SEL_WID);
+		}
+
 		rdma_write_reg_bits(devp->rdma_handle, AFBCE_ENABLE, 0, 8, 1);
 		rdma_write_reg_bits(devp->rdma_handle, VDIN_MISC_CTRL,
 			0, VDIN0_OUT_AFBCE_BIT, 1);
 		rdma_write_reg_bits(devp->rdma_handle, VDIN_MISC_CTRL,
 			1, VDIN0_OUT_MIF_BIT, 1);
 	} else if (sel == VDIN_OUTPUT_TO_AFBCE) {
+		if (is_meson_tm2_cpu()) {
+			rdma_write_reg_bits(devp->rdma_handle,
+				VDIN_TOP_DOUBLE_CTRL, WR_SEL_DIS,
+				MIF0_OUT_SEL_BIT, VDIN_REORDER_SEL_WID);
+			rdma_write_reg_bits(devp->rdma_handle,
+				VDIN_TOP_DOUBLE_CTRL, WR_SEL_VDIN0_NOR,
+				AFBCE_OUT_SEL_BIT, VDIN_REORDER_SEL_WID);
+		}
+
 		rdma_write_reg_bits(devp->rdma_handle, VDIN_MISC_CTRL,
 			0, VDIN0_OUT_MIF_BIT, 1);
 		rdma_write_reg_bits(devp->rdma_handle, VDIN_MISC_CTRL,
--- a/drivers/amlogic/media/vin/tvin/vdin/vdin_canvas.c
+++ b/drivers/amlogic/media/vin/tvin/vdin/vdin_canvas.c
@@ -61,12 +61,12 @@ MODULE_PARM_DESC(dolby_size_byte, "dolby_size_byte.\n");

 const unsigned int vdin_canvas_ids[2][VDIN_CANVAS_MAX_CNT] = {
 	{
-		38, 39, 40, 41, 42,
-		43, 44, 45, 46,
+		0x26, 0x27, 0x28, 0x29, 0x2a,
+		0x2b, 0x2c, 0x2d, 0x2e, 0x2f
 	},
 	{
-		47, 48, 49, 50, 51,
-		52, 53, 54, 55,
+		0x30, 0x31, 0x32, 0x33, 0x34,
+		0x35, 0x36, 0x37, 0x38, 0x39
 	},
 };

--- a/drivers/amlogic/media/vin/tvin/vdin/vdin_ctl.c
+++ b/drivers/amlogic/media/vin/tvin/vdin/vdin_ctl.c
@@ -2904,6 +2904,16 @@ void vdin_set_default_regmap(unsigned int offset)
 		wr(offset, VDIN_LFIFO_CTRL,     0x00000f00);
 	else if (is_meson_tm2_cpu()) {
 		wr(offset, VDIN_LFIFO_CTRL,     0xc0020f00);
+
+		/*set vdin0 out to mif0 normal begin*/
+		if (offset == 0) {
+			wr_bits(0, VDIN_TOP_DOUBLE_CTRL, WR_SEL_DIS,
+				AFBCE_OUT_SEL_BIT, VDIN_REORDER_SEL_WID);
+			wr_bits(0, VDIN_TOP_DOUBLE_CTRL, WR_SEL_VDIN0_NOR,
+				MIF0_OUT_SEL_BIT, VDIN_REORDER_SEL_WID);
+		}
+		/*set vdin0 out to mif0 normal end*/
+
 		wr(offset, VDIN_HDR2_MATRIXI_EN_CTRL, 0);
 	} else
 		wr(offset, VDIN_LFIFO_CTRL,     0x00000780);
@@ -4186,6 +4196,7 @@ int vdin_event_cb(int type, void *data, void *op_arg)
 {
 	unsigned long flags;
 	struct vf_pool *p;
+	struct vdin_dev_s *devp = vdin_get_dev(0);

 	if (!op_arg) {
 		if (vdin_ctl_dbg&(1<<3))
@@ -4246,7 +4257,7 @@ int vdin_event_cb(int type, void *data, void *op_arg)
 					__func__, index_disp);
 			return -1;
 		}
-		if (game_mode)
+		if (game_mode || devp->skip_disp_md_check)
 			req->disp_mode = VFRAME_DISP_MODE_NULL;
 		else
 			req->disp_mode = p->disp_mode[index_disp];
@@ -4257,7 +4268,6 @@ int vdin_event_cb(int type, void *data, void *op_arg)
 				__func__, type, index_disp, req->disp_mode,
 				req->req_mode);
 	} else if (type & VFRAME_EVENT_RECEIVER_NEED_NO_COMP) {
-		struct vdin_dev_s *devp = vdin_get_dev(0);
 		unsigned int *cnt;

 		/* use for debug */
--- a/drivers/amlogic/media/vin/tvin/vdin/vdin_ctl.h
+++ b/drivers/amlogic/media/vin/tvin/vdin/vdin_ctl.h
@@ -37,6 +37,14 @@ enum vdin_output_mif_e {
 	VDIN_OUTPUT_TO_AFBCE = 1,
 };

+enum wr_sel_vdin_e {
+	WR_SEL_DIS = 0,
+	WR_SEL_VDIN0_NOR = 1,
+	WR_SEL_VDIN0_SML = 2,
+	WR_SEL_VDIN1_NOR = 3,
+	WR_SEL_VDIN1_SML = 4,
+};
+
 /* *********************************************************************** */
 /* *** enum definitions ********************************************* */
 /* *********************************************************************** */
--- a/drivers/amlogic/media/vin/tvin/vdin/vdin_debug.c
+++ b/drivers/amlogic/media/vin/tvin/vdin/vdin_debug.c
@@ -2203,7 +2203,16 @@ start_chk:
 			vdin_check_vdi6_afifo_overflow(devp->addr_offset));
 	else if (!strcmp(parm[0], "vdi6_afifo_clear"))
 		vdin_clear_vdi6_afifo_overflow_flg(devp->addr_offset);
-	else
+	else if (!strcmp(parm[0], "skip_frame_check")) {
+		if (parm[1] != NULL) {
+			if (kstrtouint(parm[1], 10, &devp->skip_disp_md_check)
+				== 0)
+				pr_info("skip frame check: %d\n",
+					devp->skip_disp_md_check);
+		} else
+			pr_info("skip frame check para err, ori: %d\n",
+				devp->skip_disp_md_check);
+	} else
 		pr_info("unknown command\n");

 	kfree(buf_orig);
--- a/drivers/amlogic/media/vin/tvin/vdin/vdin_drv.c
+++ b/drivers/amlogic/media/vin/tvin/vdin/vdin_drv.c
@@ -3120,7 +3120,6 @@ static int vdin_drv_probe(struct platform_device *pdev)
 	int ret = 0;
 	struct vdin_dev_s *vdevp;
 	struct resource *res;
-	unsigned int urgent_en = 0;
 	unsigned int bit_mode = VDIN_WR_COLOR_DEPTH_8BIT;
 	/* const void *name; */
 	/* int offset, size; */
@@ -3279,28 +3278,26 @@ static int vdin_drv_probe(struct platform_device *pdev)
 	}

 	/*vdin urgent en*/
-	ret = of_property_read_u32(pdev->dev.of_node,
-			"urgent_en", &urgent_en);
-	if (ret) {
-		vdevp->urgent_en = 0;
-		pr_info("no urgent_en found\n");
-	} else
-		vdevp->urgent_en = urgent_en;
+	vdevp->urgent_en = of_property_read_bool(pdev->dev.of_node,
+		"urgent_en");
+
 	/* init vdin parameters */
 	vdevp->flags = VDIN_FLAG_NULL;
-	vdevp->flags &= (~VDIN_FLAG_FS_OPENED);
 	mutex_init(&vdevp->fe_lock);
 	spin_lock_init(&vdevp->isr_lock);
 	spin_lock_init(&vdevp->hist_lock);
 	vdevp->frontend = NULL;

-	/* @todo vdin_addr_offset */
-	if (is_meson_gxbb_cpu() && vdevp->index)
-		vdin_addr_offset[vdevp->index] = 0x70;
-	else if (cpu_after_eq(MESON_CPU_MAJOR_ID_G12A) && vdevp->index)
-		vdin_addr_offset[vdevp->index] = 0x100;
+	/* vdin_addr_offset */
+	if (vdevp->index == 1) {
+		if (is_meson_gxbb_cpu())
+			vdin_addr_offset[1] = 0x70;
+		else if (cpu_after_eq(MESON_CPU_MAJOR_ID_G12A))
+			vdin_addr_offset[1] = 0x100;
+	}
+
 	vdevp->addr_offset = vdin_addr_offset[vdevp->index];
-	vdevp->flags = 0;
+
 	/*canvas align number*/
 	if (cpu_after_eq(MESON_CPU_MAJOR_ID_G12A))
 		vdevp->canvas_align = 64;
--- a/drivers/amlogic/media/vin/tvin/vdin/vdin_drv.h
+++ b/drivers/amlogic/media/vin/tvin/vdin/vdin_drv.h
@@ -86,7 +86,7 @@
 #define VDIN_BYPASS_STOP_CHECK          0x00000001
 #define VDIN_BYPASS_CYC_CHECK           0x00000002
 #define VDIN_BYPASS_VGA_CHECK           0x00000008
-#define VDIN_CANVAS_MAX_CNT				9
+#define VDIN_CANVAS_MAX_CNT	10

 /*values of vdin game mode process flag */
 /*enable*/
@@ -418,6 +418,7 @@ struct vdin_dev_s {

 	/*atv non-std signal,force drop the field if previous already dropped*/
 	unsigned int interlace_force_drop;
+	unsigned int skip_disp_md_check;
 };

 struct vdin_hist_s {
--- a/drivers/amlogic/media/vin/tvin/vdin/vdin_regs.h
+++ b/drivers/amlogic/media/vin/tvin/vdin/vdin_regs.h
@@ -238,6 +238,9 @@
 #define VDIN_MATRIX_PRE_OFFSET2     ((0x1219))/* + 0xd0100000) */
 /* 12:0 lfifo_buf_size */
 #define VDIN_LFIFO_CTRL             ((0x121a))/* + 0xd0100000) */
+#define LFIFO_BUF_SIZE_BIT	0
+#define LFIFO_BUF_SIZE_WID	12
+
 #define VDIN_COM_GCLK_CTRL          ((0x121b))/* + 0xd0100000) */
 /* 12:0 VDIN input interface width minus 1,
 * before the window function, after the de decimation
@@ -720,6 +723,43 @@

 #define VDIN_WRARB_REQEN_SLV       0x12c1

+/*tm2 new add begin*/
+#define VDIN_VSHRK_SIZE_M1	0x12d9
+#define VSHRK_IN_HSIZE_BIT	0
+#define VSHRK_IN_HSIZE_WID	13
+#define VSHRK_IN_VSIZE_BIT	16
+#define VSHRK_IN_VSIZE_WID	13
+
+#define VDIN_HSK_CTRL	0x12ef
+#define HSK_MD_BIT	16
+#define HSK_MD_WID	7
+#define HSK_HSIZE_IN_BIT	0
+#define HSK_HSIZE_IN_WID	13
+
+#define VDIN2_WR_CTRL	0x4101
+#define VDIN2_WR_CVS_ADDR_BIT	0
+#define VDIN2_WR_CVS_ADDR_WID	8
+
+#define VDIN2_WR_CTRL2	0x4102
+#define VDIN2_WR_H_START_END	0x4103
+#define VDIN2_WR_V_START_END	0x4104
+
+/*[15:0] vdin reorder sel
+ *0:disable, 1:vdin0 normal, 2:vdin0 small, 3:vdin1 normal, 4:vdin1 small
+ */
+#define VDIN_TOP_DOUBLE_CTRL	0x410b
+#define VDIN_REORDER_SEL_WID	4
+/*[3:0] afbce sel*/
+#define AFBCE_OUT_SEL_BIT	0
+/*[7:4] wr mif 0 sel*/
+#define MIF0_OUT_SEL_BIT	4
+/*[11:8] wr mif 1 sel*/
+#define MIF1_OUT_SEL_BIT	8
+/*[15:12] wr mif 2 sel*/
+#define MIF2_OUT_SEL_BIT	12
+
+/*tm2 new add end*/
+
 /* #define VDIN_SCALE_COEF_IDX                        0x1200 */
 /* #define VDIN_SCALE_COEF                            0x1201 */

@@ -1065,10 +1105,6 @@
 #define MATRIX_PRE_OFFSET2_BIT          0
 #define MATRIX_PRE_OFFSET2_WID          11   /* s8.2 */

-/* #define VDIN_LFIFO_CTRL                         0x121a */
-#define LFIFO_BUF_SIZE_BIT              0
-#define LFIFO_BUF_SIZE_WID              12
-
 /* #define VDIN_COM_GCLK_CTRL                      0x121b */
 #define COM_GCLK_BLKBAR_BIT             14
 #define COM_GCLK_BLKBAR_WID             2    /* 00: auto, 01: off, 1x: on */