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phy: rockchip: naneng-combphy: support to disable u3 port

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This patch support to disable u3 root port for USB3.0 controller
if needed. Such as RK3568 EVB6 USB3.0 OTG1 xHCI controller, it
only used USB2.0 PHY, so we need to disable u3 port by set the
xHCI u3 port number to zero and select the clk_usb3otg0_utmi for
source clk at the same time.

Change-Id: I4aee7cc0d2947e478ff7437e47e329411e67297c
Signed-off-by: William Wu <william.wu@rock-chips.com>
This commit is contained in:
William Wu
2020-11-24 15:26:03 +08:00
committed by Tao Huang
parent 4ae0b40f64
commit 70192edddf
1 changed files with 11 additions and 0 deletions
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11
drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
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@@ -53,6 +53,8 @@ struct rockchip_combphy_grfcfg {
struct combphy_reg con2_for_sata;
struct combphy_reg con3_for_sata;
struct combphy_reg pipe_con0_for_sata;
struct combphy_reg u3otg0_port_en;
struct combphy_reg u3otg1_port_en;
};
struct rockchip_combphy_cfg {
@@ -273,6 +275,13 @@ static int rockchip_combphy_probe(struct platform_device *pdev)
return PTR_ERR(priv->phy_grf);
}
if (device_property_present(dev, "rockchip,dis-u3otg0-port"))
param_write(priv->pipe_grf, &phy_cfg->grfcfg->u3otg0_port_en,
false);
else if (device_property_present(dev, "rockchip,dis-u3otg1-port"))
param_write(priv->pipe_grf, &phy_cfg->grfcfg->u3otg1_port_en,
false);
priv->dev = dev;
priv->mode = PHY_NONE;
priv->cfg = phy_cfg;
@@ -412,6 +421,8 @@ static const struct rockchip_combphy_grfcfg rk3568_combphy_grfcfgs = {
.con2_for_sata = { 0x0008, 15, 0, 0x00, 0x80c3 },
.con3_for_sata = { 0x000c, 15, 0, 0x00, 0x4402 },
.pipe_con0_for_sata = { 0x0000, 15, 0, 0x00, 0x2220 },
.u3otg0_port_en = { 0x0104, 15, 0, 0x0181, 0x1100 },
.u3otg1_port_en = { 0x0144, 15, 0, 0x0181, 0x1100 },
};
static const struct clk_bulk_data rk3568_clks[] = {