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dt-bindings: phy-rockchip-naneng-combphy: add property to disable u3 port

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This patch add new property to disable u3 root port for
usb3.0 controller if we want to force the controller
to u2 only mode.

Change-Id: I53da3a7816585f1d3f9ac7fd3ee5ba8ba323eff1
Signed-off-by: William Wu <william.wu@rock-chips.com>
This commit is contained in:
William Wu
2020-11-24 15:18:02 +08:00
committed by Tao Huang
parent d85facab5d
commit 4ae0b40f64
1 changed files with 2 additions and 0 deletions
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2
Documentation/devicetree/bindings/phy/phy-rockchip-naneng-combphy.txt
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@@ -17,6 +17,8 @@ Optional properties:
- assigned-clock-parents : parent of clk_xxx_osc or clk_xxx_div.
Refer to clk/clock-bindings.txt for generic clock
consumer properties.
- rockchip,dis-u3otg0-port: when set, disable the u3 root port of otg0 host.
- rockchip,dis-u3otg1-port: when set, disable the u3 root port of otg1 host.
Example: