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Merge 9805529ec5 ("Merge tag 'arm-soc-dt-5.11' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc") into android-mainline

Browse Source 
Steps on the way to 5.11-rc1

Change-Id: I6d77c7f2e7b3ccda9570946e3ad4244a14eb1f2f
Signed-off-by: Greg Kroah-Hartman <gregkh@google.com>
This commit is contained in:
Greg Kroah-Hartman
2020-12-21 09:39:21 +01:00
parent d027702167 9805529ec5
commit 701c8a1a2f
688 changed files with 39042 additions and 3452 deletions
Download Patch File Download Diff File Expand all files Collapse all files

10
Documentation/devicetree/bindings/Makefile
View File

@@ -27,17 +27,17 @@ find_cmd = find $(srctree)/$(src) \( -name '*.yaml' ! \
-name '*.example.dt.yaml' \)
quiet_cmd_yamllint = LINT $(src)
cmd_yamllint = $(find_cmd) | \
xargs $(DT_SCHEMA_LINT) -f parsable -c $(srctree)/$(src)/.yamllint
cmd_yamllint = ($(find_cmd) | \
xargs $(DT_SCHEMA_LINT) -f parsable -c $(srctree)/$(src)/.yamllint) || true
quiet_cmd_chk_bindings = CHKDT $@
cmd_chk_bindings = $(find_cmd) | \
xargs -n200 -P$$(nproc) $(DT_DOC_CHECKER) -u $(srctree)/$(src)
cmd_chk_bindings = ($(find_cmd) | \
xargs -n200 -P$$(nproc) $(DT_DOC_CHECKER) -u $(srctree)/$(src)) || true
quiet_cmd_mk_schema = SCHEMA $@
cmd_mk_schema = f=$$(mktemp) ; \
$(if $(DT_MK_SCHEMA_FLAGS), \
echo $(real-prereqs), \
printf '%s\n' $(real-prereqs), \
$(find_cmd)) > $$f ; \
$(DT_MK_SCHEMA) -j $(DT_MK_SCHEMA_FLAGS) @$$f > $@ ; \
rm -f $$f

38
Documentation/devicetree/bindings/arm/bcm/brcm,bcm4908.yaml Normal file
View File

@@ -0,0 +1,38 @@
# SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/arm/bcm/brcm,bcm4908.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Broadcom BCM4908 device tree bindings
description:
Broadcom BCM4906 / BCM4908 / BCM49408 Wi-Fi/network SoCs with Brahma CPUs.
maintainers:
- Rafał Miłecki <rafal@milecki.pl>
properties:
$nodename:
const: '/'
compatible:
oneOf:
- description: BCM4906 based boards
items:
- const: brcm,bcm4906
- const: brcm,bcm4908
- description: BCM4908 based boards
items:
- enum:
- asus,gt-ac5300
- const: brcm,bcm4908
- description: BCM49408 based boards
items:
- const: brcm,bcm49408
- const: brcm,bcm4908
additionalProperties: true
...

12
Documentation/devicetree/bindings/arm/freescale/fsl,scu.txt
View File

@@ -89,7 +89,10 @@ Required properties:
"fsl,imx8qm-clock"
"fsl,imx8qxp-clock"
followed by "fsl,scu-clk"
- #clock-cells: Should be 1. Contains the Clock ID value.
- #clock-cells: Should be either
2: Contains the Resource and Clock ID value.
or
1: Contains the Clock ID value. (DEPRECATED)
- clocks: List of clock specifiers, must contain an entry for
each required entry in clock-names
- clock-names: Should include entries "xtal_32KHz", "xtal_24MHz"
@@ -208,7 +211,7 @@ firmware {
clk: clk {
compatible = "fsl,imx8qxp-clk", "fsl,scu-clk";
#clock-cells = <1>;
#clock-cells = <2>;
};
iomuxc {
@@ -263,8 +266,7 @@ serial@5a060000 {
...
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lpuart0>;
clocks = <&clk IMX8QXP_UART0_CLK>,
<&clk IMX8QXP_UART0_IPG_CLK>;
clock-names = "per", "ipg";
clocks = <&uart0_clk IMX_SC_R_UART_0 IMX_SC_PM_CLK_PER>;
clock-names = "ipg";
power-domains = <&pd IMX_SC_R_UART_0>;
};

360
Documentation/devicetree/bindings/arm/fsl.yaml
View File

@@ -33,16 +33,57 @@ properties:
items:
- enum:
- fsl,imx25-pdk
- karo,imx25-tx25
- const: fsl,imx25
- description: i.MX27 Product Development Kit
- description: i.MX25 Eukrea CPUIMX25 Boards
items:
- enum:
- eukrea,mbimxsd25-baseboard # Eukrea MBIMXSD25
- const: eukrea,cpuimx25
- const: fsl,imx25
- description: i.MX25 Eukrea MBIMXSD25 Boards
items:
- enum:
- eukrea,mbimxsd25-baseboard-cmo-qvga
- eukrea,mbimxsd25-baseboard-dvi-svga
- eukrea,mbimxsd25-baseboard-dvi-vga
- const: eukrea,mbimxsd25-baseboard
- const: eukrea,cpuimx25
- const: fsl,imx25
- description: i.MX27 based Boards
items:
- enum:
- armadeus,imx27-apf27 # APF27 SoM
- armadeus,imx27-apf27dev # APF27 SoM on APF27Dev board
- fsl,imx27-pdk
- const: fsl,imx27
- description: i.MX27 APF27 SoM Board
items:
- const: armadeus,imx27-apf27dev
- const: armadeus,imx27-apf27
- const: fsl,imx27
- description: i.MX27 Eukrea CPUIMX27 SoM Board
items:
- const: eukrea,mbimxsd27-baseboard
- const: eukrea,cpuimx27
- const: fsl,imx27
- description: i.MX27 Phytec pca100 Board
items:
- const: phytec,imx27-pca100-rdk
- const: phytec,imx27-pca100
- const: fsl,imx27
- description: i.MX27 Phytec pcm970 Board
items:
- const: phytec,imx27-pcm970
- const: phytec,imx27-pcm038
- const: fsl,imx27
- description: i.MX28 based Boards
items:
- enum:
@@ -88,13 +129,33 @@ properties:
- kobo,aura
- const: fsl,imx50
- description: i.MX51 Babbage Board
- description: i.MX51 based Boards
items:
- enum:
- armadeus,imx51-apf51 # APF51 SoM
- armadeus,imx51-apf51dev # APF51 SoM on APF51Dev board
- armadeus,imx51-apf51 # Armadeus Systems APF51 module
- fsl,imx51-babbage
- technologic,imx51-ts4800
- zii,imx51-scu3-esb
- zii,imx51-scu2-mezz
- zii,imx51-rdu1
- const: fsl,imx51
- description: i.MX51 based Armadeus Systems APF51Dev Board
items:
- const: armadeus,imx51-apf51dev
- const: armadeus,imx51-apf51
- const: fsl,imx51
- description: i.MX51 based Digi ConnectCore CC(W)-MX51 JSK Board
items:
- const: digi,connectcore-ccxmx51-jsk
- const: digi,connectcore-ccxmx51-som
- const: fsl,imx51
- description: i.MX51 based Eukrea CPUIMX51 Board
items:
- const: eukrea,mbimxsd51
- const: eukrea,cpuimx51
- const: fsl,imx51
- description: i.MX53 based Boards
@@ -104,36 +165,111 @@ properties:
- fsl,imx53-ard
- fsl,imx53-evk
- fsl,imx53-qsb
- fsl,imx53-qsrb # Freescale i.MX53 Quick Start-R Board
- fsl,imx53-smd
- ge,imx53-cpuvo # General Electric CS ONE
- inversepath,imx53-usbarmory # Inverse Path USB armory
- karo,tx53 # Ka-Ro electronics TX53 module
- kiebackpeter,imx53-ddc # K+P imx53 DDC
- kiebackpeter,imx53-hsc # K+P imx53 HSC
- menlo,m53menlo
- voipac,imx53-dmm-668 # Voipac i.MX53 X53-DMM-668
- const: fsl,imx53
- description: i.MX53 based Aries/DENX M53EVK Board
items:
- const: aries,imx53-m53evk
- const: denx,imx53-m53evk
- const: fsl,imx53
- description: i.MX53 based TQ MBa53 Board
items:
- const: tq,mba53
- const: tq,tqma53
- const: fsl,imx53
- description: i.MX6Q based Boards
items:
- enum:
- armadeus,imx6q-apf6 # APF6 (Quad/Dual) SoM
- armadeus,imx6q-apf6dev # APF6 (Quad/Dual) SoM on APF6Dev board
- auvidea,h100 # Auvidea H100
- boundary,imx6q-nitrogen6_max
- boundary,imx6q-nitrogen6_som2
- boundary,imx6q-nitrogen6x
- compulab,cm-fx6 # CompuLab CM-FX6
- dmo,imx6q-edmqmx6 # Data Modul eDM-QMX6 Board
- embest,imx6q-marsboard # Embest MarS Board i.MX6Dual
- emtrion,emcon-mx6 # emCON-MX6D or emCON-MX6Q SoM
- emtrion,emcon-mx6-avari # emCON-MX6D or emCON-MX6Q SoM on Avari Base
- engicam,imx6-icore # Engicam i.CoreM6 Starter Kit
- engicam,imx6-icore-rqs # Engicam i.CoreM6 RQS Starter Kit
- fsl,imx6q-arm2
- fsl,imx6q-sabreauto
- fsl,imx6q-sabrelite
- fsl,imx6q-sabresd
- karo,imx6q-tx6q # Ka-Ro electronics TX6Q Modules
- kiebackpeter,imx6q-tpc # K+P i.MX6 Quad TPC Board
- kontron,imx6q-samx6i # Kontron i.MX6 Dual/Quad SMARC Module
- kosagi,imx6q-novena # Kosagi Novena Dual/Quad
- logicpd,imx6q-logicpd
- lwn,display5 # Liebherr Display5 i.MX6 Quad Board
- lwn,mccmon6 # Liebherr Monitor6 i.MX6 Quad Board
- nutsboard,imx6q-pistachio # NutsBoard i.MX6 Quad Pistachio
- microsys,sbc6x # MicroSys sbc6x board
- poslab,imx6q-savageboard # Poslab SavageBoard Quad
- prt,prti6q # Protonic PRTI6Q board
- prt,prtwd2 # Protonic WD2 board
- rex,imx6q-rex-pro # Rex Pro i.MX6 Quad Board
- solidrun,cubox-i/q # SolidRun Cubox-i Dual/Quad
- solidrun,hummingboard/q
- solidrun,hummingboard2/q
- tbs,imx6q-tbs2910 # TBS2910 Matrix ARM mini PC
- technexion,imx6q-pico-dwarf # TechNexion i.MX6Q Pico-Dwarf
- technexion,imx6q-pico-hobbit # TechNexion i.MX6Q Pico-Hobbit
- technexion,imx6q-pico-nymph # TechNexion i.MX6Q Pico-Nymph
- technexion,imx6q-pico-pi # TechNexion i.MX6Q Pico-Pi
- technologic,imx6q-ts4900
- technologic,imx6q-ts7970
- toradex,apalis_imx6q # Apalis iMX6 Module
- toradex,apalis_imx6q-eval # Apalis iMX6 Module on Apalis Evaluation Board
- toradex,apalis_imx6q-ixora # Apalis iMX6 Module on Ixora
- toradex,apalis_imx6q-ixora-v1.1 # Apalis iMX6 Module on Ixora V1.1
- toradex,apalis_imx6q # Apalis iMX6 Module
- udoo,imx6q-udoo # Udoo i.MX6 Quad Board
- uniwest,imx6q-evi # Uniwest Evi
- variscite,dt6customboard
- wand,imx6q-wandboard # Wandboard i.MX6 Quad Board
- zealz,imx6q-gk802 # Zealz GK802
- zii,imx6q-zii-rdu2 # ZII RDU2 Board
- const: fsl,imx6q
- description: i.MX6Q Advantech DMS-BA16 Boards
items:
- enum:
- advantech,imx6q-dms-ba16 # Advantech DMS-BA16
- ge,imx6q-b450v3 # General Electric B450v3
- ge,imx6q-b650v3 # General Electric B650v3
- ge,imx6q-b850v3 # General Electric B850v3
- const: advantech,imx6q-ba16
- const: fsl,imx6q
- description: i.MX6Q Armadeus APF6 Boards
items:
- const: armadeus,imx6q-apf6dev
- const: armadeus,imx6q-apf6
- const: fsl,imx6q
- description: i.MX6Q CompuLab Utilite Pro Board
items:
- const: compulab,utilite-pro
- const: compulab,cm-fx6
- const: fsl,imx6q
- description: i.MX6Q DFI FS700-M60-6QD Board
items:
- const: dfi,fs700-m60-6qd
- const: dfi,fs700e-m60
- const: fsl,imx6q
- description: i.MX6Q DHCOM Premium Developer Kit Board
items:
- const: dh,imx6q-dhcom-pdk2
- const: dh,imx6q-dhcom-som
- const: fsl,imx6q
- description: i.MX6Q Gateworks Ventana Boards
@@ -172,11 +308,32 @@ properties:
- const: phytec,imx6q-pfla02 # PHYTEC phyFLEX-i.MX6 Quad
- const: fsl,imx6q
- description: i.MX6Q Boards with Toradex Apalis iMX6Q/D Module
items:
- enum:
- toradex,apalis_imx6q-ixora # Apalis iMX6Q/D Module on Ixora Carrier Board
- toradex,apalis_imx6q-eval # Apalis iMX6Q/D Module on Apalis Evaluation Board
- const: toradex,apalis_imx6q
- const: fsl,imx6q
- description: i.MX6Q Toradex Apalis iMX6Q/D Module on Ixora Carrier Board V1.1
items:
- const: toradex,apalis_imx6q-ixora-v1.1
- const: toradex,apalis_imx6q-ixora
- const: toradex,apalis_imx6q
- const: fsl,imx6q
- description: i.MX6QP based Boards
items:
- enum:
- boundary,imx6qp-nitrogen6_max
- boundary,imx6qp-nitrogen6_som2
- fsl,imx6qp-sabreauto # i.MX6 Quad Plus SABRE Automotive Board
- fsl,imx6qp-sabresd # i.MX6 Quad Plus SABRE Smart Device Board
- karo,imx6qp-tx6qp # Ka-Ro electronics TX6QP-8037 Module
- prt,prtwd3 # Protonic WD3 board
- wand,imx6qp-wandboard # Wandboard i.MX6 QuadPlus Board
- zii,imx6qp-zii-rdu2 # ZII RDU2+ Board
- const: fsl,imx6qp
- description: i.MX6QP PHYTEC phyBOARD-Mira
@@ -189,32 +346,59 @@ properties:
- description: i.MX6DL based Boards
items:
- enum:
- armadeus,imx6dl-apf6 # APF6 (Solo) SoM
- armadeus,imx6dl-apf6dev # APF6 (Solo) SoM on APF6Dev board
- abb,aristainetos-imx6dl-4 # aristainetos i.MX6 Dual Lite Board 4
- abb,aristainetos-imx6dl-7 # aristainetos i.MX6 Dual Lite Board 7
- abb,aristainetos2-imx6dl-4 # aristainetos2 i.MX6 Dual Lite Board 4
- abb,aristainetos2-imx6dl-7 # aristainetos2 i.MX6 Dual Lite Board 7
- alt,alti6p # Altesco I6P Board
- boundary,imx6dl-nit6xlite # Boundary Devices Nitrogen6 Lite
- boundary,imx6dl-nitrogen6x # Boundary Devices Nitrogen6x
- bticino,imx6dl-mamoj # BTicino i.MX6DL Mamoj
- eckelmann,imx6dl-ci4x10
- emtrion,emcon-mx6 # emCON-MX6S or emCON-MX6DL SoM
- emtrion,emcon-mx6-avari # emCON-MX6S or emCON-MX6DL SoM on Avari Base
- engicam,imx6-icore # Engicam i.CoreM6 Starter Kit
- engicam,imx6-icore-rqs # Engicam i.CoreM6 RQS Starter Kit
- fsl,imx6dl-sabreauto # i.MX6 DualLite/Solo SABRE Automotive Board
- fsl,imx6dl-sabrelite # i.MX6 DualLite SABRE Lite Board
- fsl,imx6dl-sabresd # i.MX6 DualLite SABRE Smart Device Board
- karo,imx6dl-tx6dl # Ka-Ro electronics TX6U Modules
- kontron,imx6dl-samx6i # Kontron i.MX6 Solo SMARC Module
- poslab,imx6dl-savageboard # Poslab SavageBoard Dual
- prt,prtrvt # Protonic RVT board
- prt,prtvt7 # Protonic VT7 board
- rex,imx6dl-rex-basic # Rex Basic i.MX6 Dual Lite Board
- riot,imx6s-riotboard # RIoTboard i.MX6S
- solidrun,cubox-i/dl # SolidRun Cubox-i Solo/DualLite
- solidrun,hummingboard/dl
- solidrun,hummingboard2/dl # SolidRun HummingBoard2 Solo/DualLite
- technexion,imx6dl-pico-dwarf # TechNexion i.MX6DL Pico-Dwarf
- technexion,imx6dl-pico-hobbit # TechNexion i.MX6DL Pico-Hobbit
- technexion,imx6dl-pico-nymph # TechNexion i.MX6DL Pico-Nymph
- technexion,imx6dl-pico-pi # TechNexion i.MX6DL Pico-Pi
- technologic,imx6dl-ts4900
- technologic,imx6dl-ts7970
- toradex,colibri_imx6dl # Colibri iMX6 Module
- toradex,colibri_imx6dl-v1_1 # Colibri iMX6 Module V1.1
- toradex,colibri_imx6dl-eval-v3 # Colibri iMX6 Module on Colibri Evaluation Board V3
- toradex,colibri_imx6dl-v1_1-eval-v3 # Colibri iMX6 Module V1.1 on Colibri Evaluation Board V3
- udoo,imx6dl-udoo # Udoo i.MX6 Dual-lite Board
- vdl,lanmcu # Van der Laan LANMCU board
- wand,imx6dl-wandboard # Wandboard i.MX6 Dual Lite Board
- ysoft,imx6dl-yapp4-draco # i.MX6 DualLite Y Soft IOTA Draco board
- ysoft,imx6dl-yapp4-hydra # i.MX6 DualLite Y Soft IOTA Hydra board
- ysoft,imx6dl-yapp4-orion # i.MX6 DualLite Y Soft IOTA Orion board
- ysoft,imx6dl-yapp4-ursa # i.MX6 Solo Y Soft IOTA Ursa board
- const: fsl,imx6dl
- description: i.MX6DL based Armadeus AFP6 Board
items:
- const: armadeus,imx6dl-apf6dev
- const: armadeus,imx6dl-apf6 # APF6 (Solo) SoM
- const: fsl,imx6dl
- description: i.MX6DL based DFI FS700-M60-6DL Board
items:
- const: dfi,fs700-m60-6dl
- const: dfi,fs700e-m60
- const: fsl,imx6dl
- description: i.MX6DL Gateworks Ventana Boards
items:
- enum:
@@ -250,12 +434,29 @@ properties:
- const: phytec,imx6dl-pfla02 # PHYTEC phyFLEX-i.MX6 Quad
- const: fsl,imx6dl
- description: i.MX6DL Toradex Colibri iMX6 Module on Colibri
Evaluation Board V3
items:
- const: toradex,colibri_imx6dl-eval-v3
- const: toradex,colibri_imx6dl # Colibri iMX6 Module
- const: fsl,imx6dl
- description: i.MX6DL Toradex Colibri iMX6 Module V1.1 on Colibri
Evaluation Board V3
items:
- const: toradex,colibri_imx6dl-v1_1-eval-v3
- const: toradex,colibri_imx6dl-v1_1 # Colibri iMX6 Module V1.1
- const: toradex,colibri_imx6dl-eval-v3
- const: toradex,colibri_imx6dl # Colibri iMX6 Module
- const: fsl,imx6dl
- description: i.MX6SL based Boards
items:
- enum:
- fsl,imx6sl-evk # i.MX6 SoloLite EVK Board
- kobo,tolino-shine2hd
- kobo,tolino-shine3
- revotics,imx6sl-warp # Revotics WaRP Board
- const: fsl,imx6sl
- description: i.MX6SLL based Boards
@@ -268,17 +469,23 @@ properties:
- description: i.MX6SX based Boards
items:
- enum:
- boundary,imx6sx-nitrogen6sx
- fsl,imx6sx-sabreauto # i.MX6 SoloX Sabre Auto Board
- fsl,imx6sx-sdb # i.MX6 SoloX SDB Board
- fsl,imx6sx-sdb-reva # i.MX6 SoloX SDB Rev-A Board
- samtec,imx6sx-vining-2000 # Softing VIN|ING 2000 Board
- udoo,neobasic # UDOO Neo Basic Board
- udoo,neoextended # UDOO Neo Extended
- udoo,neofull # UDOO Neo Full
- const: fsl,imx6sx
- description: i.MX6UL based Boards
items:
- enum:
- armadeus,imx6ul-opos6ul # OPOS6UL (i.MX6UL) SoM
- armadeus,imx6ul-opos6uldev # OPOS6UL (i.MX6UL) SoM on OPOS6ULDev board
- engicam,imx6ul-geam # Engicam GEAM6UL Starter Kit
- engicam,imx6ul-isiot # Engicam Is.IoT MX6UL eMMC/NAND Starter kit
- fsl,imx6ul-14x14-evk # i.MX6 UltraLite 14x14 EVK Board
- karo,imx6ul-tx6ul # Ka-Ro electronics TXUL-0010 Module
- kontron,imx6ul-n6310-som # Kontron N6310 SOM
- kontron,imx6ul-n6311-som # Kontron N6311 SOM
- technexion,imx6ul-pico-dwarf # TechNexion i.MX6UL Pico-Dwarf
@@ -286,6 +493,26 @@ properties:
- technexion,imx6ul-pico-pi # TechNexion i.MX6UL Pico-Pi
- const: fsl,imx6ul
- description: i.MX6UL Armadeus Systems OPOS6UL SoM Board
items:
- const: armadeus,imx6ul-opos6uldev # OPOS6UL (i.MX6UL) SoM on OPOS6ULDev board
- const: armadeus,imx6ul-opos6ul # OPOS6UL (i.MX6UL) SoM
- const: fsl,imx6ul
- description: i.MX6UL Digi International ConnectCore 6UL Boards
items:
- enum:
- digi,ccimx6ulsbcexpress # Digi International ConnectCore 6UL SBC Express
- digi,ccimx6ulsbcpro # Digi International ConnectCore 6UL SBC Pro
- const: digi,ccimx6ulsom
- const: fsl,imx6ul
- description: i.MX6UL Grinn liteBoard
items:
- const: grinn,imx6ul-liteboard
- const: grinn,imx6ul-litesom
- const: fsl,imx6ul
- description: i.MX6UL PHYTEC phyBOARD-Segin
items:
- enum:
@@ -317,8 +544,6 @@ properties:
- description: i.MX6ULL based Boards
items:
- enum:
- armadeus,imx6ull-opos6ul # OPOS6UL (i.MX6ULL) SoM
- armadeus,imx6ull-opos6uldev # OPOS6UL (i.MX6ULL) SoM on OPOS6ULDev board
- fsl,imx6ull-14x14-evk # i.MX6 UltraLiteLite 14x14 EVK Board
- kontron,imx6ull-n6411-som # Kontron N6411 SOM
- myir,imx6ull-mys-6ulx-eval # MYiR Tech iMX6ULL Evaluation Board
@@ -326,6 +551,12 @@ properties:
- toradex,colibri-imx6ull-wifi-eval # Colibri iMX6ULL Wi-Fi / BT Module on Colibri Eval Board
- const: fsl,imx6ull
- description: i.MX6ULL Armadeus Systems OPOS6ULDev Board
items:
- const: armadeus,imx6ull-opos6uldev # OPOS6UL (i.MX6ULL) SoM on OPOS6ULDev board
- const: armadeus,imx6ull-opos6ul # OPOS6UL (i.MX6ULL) SoM
- const: fsl,imx6ull
- description: i.MX6ULL PHYTEC phyBOARD-Segin
items:
- enum:
@@ -351,17 +582,32 @@ properties:
- description: i.MX7S based Boards
items:
- enum:
- toradex,colibri-imx7s # Colibri iMX7 Solo Module
- toradex,colibri-imx7s-aster # Colibri iMX7 Solo Module on Aster Carrier Board
- toradex,colibri-imx7s-eval-v3 # Colibri iMX7 Solo Module on Colibri Evaluation Board V3
- tq,imx7s-mba7 # i.MX7S TQ MBa7 with TQMa7S SoM
- element14,imx7s-warp # Element14 Warp i.MX7 Board
- const: fsl,imx7s
- description: i.MX7S Boards with Toradex Colibri iMX7S Module
items:
- enum:
- toradex,colibri-imx7s-aster # Module on Aster Carrier Board
- toradex,colibri-imx7s-eval-v3 # Module on Colibri Evaluation Board V3
- const: toradex,colibri-imx7s
- const: fsl,imx7s
- description: TQ-Systems TQMa7S SoM on MBa7x board
items:
- const: tq,imx7s-mba7
- const: tq,imx7s-tqma7
- const: fsl,imx7s
- description: i.MX7D based Boards
items:
- enum:
- boundary,imx7d-nitrogen7
- compulab,cl-som-imx7 # CompuLab CL-SOM-iMX7
- fsl,imx7d-sdb # i.MX7 SabreSD Board
- fsl,imx7d-sdb-reva # i.MX7 SabreSD Rev-A Board
- kam,imx7d-flex-concentrator # Kamstrup OMNIA Flex Concentrator
- kam,imx7d-flex-concentrator-mfg # Kamstrup OMNIA Flex Concentrator in manufacturing mode
- novtech,imx7d-meerkat96 # i.MX7 Meerkat96 Board
- technexion,imx7d-pico-dwarf # TechNexion i.MX7D Pico-Dwarf
- technexion,imx7d-pico-hobbit # TechNexion i.MX7D Pico-Hobbit
@@ -376,11 +622,16 @@ properties:
# Colibri Evaluation Board V3
- toradex,colibri-imx7d-eval-v3 # Colibri iMX7 Dual Module on
# Colibri Evaluation Board V3
- tq,imx7d-mba7 # i.MX7D TQ MBa7 with TQMa7D SoM
- zii,imx7d-rmu2 # ZII RMU2 Board
- zii,imx7d-rpu2 # ZII RPU2 Board
- const: fsl,imx7d
- description: TQ-Systems TQMa7D SoM on MBa7x board
items:
- const: tq,imx7d-mba7
- const: tq,imx7d-tqma7
- const: fsl,imx7d
- description:
Compulab SBC-iMX7 is a single board computer based on the
Freescale i.MX7 system-on-chip. SBC-iMX7 is implemented with
@@ -392,6 +643,22 @@ properties:
- const: compulab,cl-som-imx7
- const: fsl,imx7d
- description: i.MX7D Boards with Toradex Colibri i.MX7D Module
items:
- enum:
- toradex,colibri-imx7d-aster # Module on Aster Carrier Board
- toradex,colibri-imx7d-eval-v3 # Module on Colibri Evaluation Board V3
- const: toradex,colibri-imx7d
- const: fsl,imx7d
- description: i.MX7D Boards with Toradex Colibri i.MX7D eMMC Module
items:
- enum:
- toradex,colibri-imx7d-emmc-aster # Module on Aster Carrier Board
- toradex,colibri-imx7d-emmc-eval-v3 # Module on Colibri Evaluation Board V3
- const: toradex,colibri-imx7d-emmc
- const: fsl,imx7d
- description: i.MX7ULP based Boards
items:
- enum:
@@ -405,9 +672,16 @@ properties:
- beacon,imx8mm-beacon-kit # i.MX8MM Beacon Development Kit
- fsl,imx8mm-ddr4-evk # i.MX8MM DDR4 EVK Board
- fsl,imx8mm-evk # i.MX8MM EVK Board
- kontron,imx8mm-n801x-som # i.MX8MM Kontron SL (N801X) SOM
- variscite,var-som-mx8mm # i.MX8MM Variscite VAR-SOM-MX8MM module
- const: fsl,imx8mm
- description: Kontron BL i.MX8MM (N801X S) Board
items:
- const: kontron,imx8mm-n801x-s
- const: kontron,imx8mm-n801x-som
- const: fsl,imx8mm
- description: Variscite VAR-SOM-MX8MM based boards
items:
- const: variscite,var-som-mx8mm-symphony
@@ -491,10 +765,26 @@ properties:
- fsl,vf600
- fsl,vf610
- fsl,vf610m4
- toradex,vf500-colibri_vf50 # Colibri VF50 Module
- toradex,vf500-colibri_vf50-on-eval # Colibri VF50 Module on Colibri Evaluation Board
- toradex,vf610-colibri_vf61 # Colibri VF61 Module
- toradex,vf610-colibri_vf61-on-eval # Colibri VF61 Module on Colibri Evaluation Board
- description: Toradex Colibri VF50 Module on Colibri Evaluation Board
items:
- const: toradex,vf500-colibri_vf50-on-eval
- const: toradex,vf500-colibri_vf50
- const: fsl,vf500
- description: VF610 based Boards
items:
- enum:
- lwn,bk4 # Liebherr BK4 controller
- phytec,vf610-cosmic # PHYTEC Cosmic/Cosmic+ Board
- fsl,vf610-twr # VF610 Tower Board
- const: fsl,vf610
- description: Toradex Colibri VF61 Module on Colibri Evaluation Board
items:
- const: toradex,vf610-colibri_vf61-on-eval
- const: toradex,vf610-colibri_vf61
- const: fsl,vf610
- description: ZII's VF610 based Boards
items:
@@ -515,6 +805,7 @@ properties:
- ebs-systart,oxalis
- fsl,ls1012a-rdb
- fsl,ls1012a-frdm
- fsl,ls1012a-frwy
- fsl,ls1012a-qds
- const: fsl,ls1012a
@@ -613,6 +904,15 @@ properties:
- enum:
- fsl,lx2160a-qds
- fsl,lx2160a-rdb
- fsl,lx2162a-qds
- const: fsl,lx2160a
- description: SolidRun LX2160A based Boards
items:
- enum:
- solidrun,clearfog-cx
- solidrun,honeycomb
- const: solidrun,lx2160a-cex7
- const: fsl,lx2160a
- description: S32V234 based Boards

4
Documentation/devicetree/bindings/arm/mediatek.yaml
View File

@@ -84,6 +84,10 @@ properties:
- enum:
- mediatek,mt8135-evbp1
- const: mediatek,mt8135
- items:
- enum:
- mediatek,mt8167-pumpkin
- const: mediatek,mt8167
- description: Google Elm (Acer Chromebook R13)
items:
- const: google,elm-rev8

40
Documentation/devicetree/bindings/arm/mstar/mstar,smpctrl.yaml Normal file
View File

@@ -0,0 +1,40 @@
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
# Copyright 2020 thingy.jp.
%YAML 1.2
---
$id: "http://devicetree.org/schemas/arm/mstar/mstar,smpctrl.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
title: MStar/SigmaStar Armv7 SoC SMP control registers
maintainers:
- Daniel Palmer <daniel@thingy.jp>
description: |
MStar/SigmaStar's Armv7 SoCs that have more than one processor
have a region of registers that allow setting the boot address
and a magic number that allows secondary processors to leave
the loop they are parked in by the boot ROM.
properties:
compatible:
items:
- enum:
- sstar,ssd201-smpctrl # SSD201/SSD202D
- const: mstar,smpctrl
reg:
maxItems: 1
required:
- compatible
- reg
additionalProperties: false
examples:
- |
smpctrl@204000 {
compatible = "sstar,ssd201-smpctrl", "mstar,smpctrl";
reg = <0x204000 0x200>;
};

6
Documentation/devicetree/bindings/arm/mstar/mstar.yaml
View File

@@ -20,6 +20,12 @@ properties:
- thingyjp,breadbee-crust # thingy.jp BreadBee Crust
- const: mstar,infinity
- description: infinity2m boards
items:
- enum:
- honestar,ssd201htv2 # Honestar SSD201_HT_V2 devkit
- const: mstar,infinity2m
- description: infinity3 boards
items:
- enum:

24
Documentation/devicetree/bindings/arm/picoxcell.txt
View File

@@ -1,24 +0,0 @@
Picochip picoXcell device tree bindings.
========================================
Required root node properties:
- compatible:
- "picochip,pc7302-pc3x3" : PC7302 development board with PC3X3 device.
- "picochip,pc7302-pc3x2" : PC7302 development board with PC3X2 device.
- "picochip,pc3x3" : picoXcell PC3X3 device based board.
- "picochip,pc3x2" : picoXcell PC3X2 device based board.
Timers required properties:
- compatible = "picochip,pc3x2-timer"
- interrupts : The single IRQ line for the timer.
- clock-freq : The frequency in HZ of the timer.
- reg : The register bank for the timer.
Note: two timers are required - one for the scheduler clock and one for the
event tick/NOHZ.
VIC required properties:
- compatible = "arm,pl192-vic".
- interrupt-controller.
- reg : The register bank for the device.
- #interrupt-cells : Must be 1.

1
Documentation/devicetree/bindings/arm/renesas.yaml
View File

@@ -245,6 +245,7 @@ properties:
- enum:
- renesas,r8a7795
- renesas,r8a7796
- renesas,r8a77961
- renesas,r8a77965
- description: R-Car M3-N (R8A77965)

23
Documentation/devicetree/bindings/arm/rockchip.yaml
View File

@@ -70,6 +70,24 @@ properties:
- const: elgin,rv1108-r1
- const: rockchip,rv1108
- description: Engicam PX30.Core C.TOUCH 2.0
items:
- const: engicam,px30-core-ctouch2
- const: engicam,px30-core
- const: rockchip,px30
- description: Engicam PX30.Core C.TOUCH 2.0 10.1" Open Frame
items:
- const: engicam,px30-core-ctouch2-of10
- const: engicam,px30-core
- const: rockchip,px30
- description: Engicam PX30.Core EDIMM2.2 Starter Kit
items:
- const: engicam,px30-core-edimm2.2
- const: engicam,px30-core
- const: rockchip,px30
- description: Firefly Firefly-RK3288
items:
- enum:
@@ -381,6 +399,11 @@ properties:
- khadas,edge-v
- const: rockchip,rk3399
- description: Kobol Helios64
items:
- const: kobol,helios64
- const: rockchip,rk3399
- description: Mecer Xtreme Mini S6
items:
- const: mecer,xms6

21
Documentation/devicetree/bindings/arm/samsung/samsung-boards.yaml
View File

@@ -14,6 +14,19 @@ properties:
const: '/'
compatible:
oneOf:
- description: S3C2416 based boards
items:
- enum:
- samsung,smdk2416 # Samsung SMDK2416
- const: samsung,s3c2416
- description: S3C6410 based boards
items:
- enum:
- friendlyarm,mini6410 # FriendlyARM Mini6410
- samsung,smdk6410 # Samsung SMDK6410
- const: samsung,s3c6410
- description: S5PV210 based boards
items:
- enum:
@@ -83,6 +96,14 @@ properties:
- const: samsung,exynos4412
- const: samsung,exynos4
- description: Samsung p4note family boards
items:
- enum:
- samsung,n8010 # Samsung GT-N8010/GT-N8013
- const: samsung,p4note
- const: samsung,exynos4412
- const: samsung,exynos4
- description: Exynos5250 based boards
items:
- enum:

4
Documentation/devicetree/bindings/arm/stm32/st,stm32-syscon.yaml
View File

@@ -21,6 +21,10 @@ properties:
- st,stm32-power-config
- st,stm32-tamp
- const: syscon
- items:
- const: st,stm32-tamp
- const: syscon
- const: simple-mfd
reg:
maxItems: 1

23
Documentation/devicetree/bindings/arm/stm32/stm32.yaml
View File

@@ -14,6 +14,20 @@ properties:
const: "/"
compatible:
oneOf:
- description: DH STM32MP1 SoM based Boards
items:
- enum:
- arrow,stm32mp157a-avenger96 # Avenger96
- dh,stm32mp153c-dhcom-drc02
- dh,stm32mp157c-dhcom-pdk2
- dh,stm32mp157c-dhcom-picoitx
- enum:
- dh,stm32mp153c-dhcom-som
- dh,stm32mp157a-dhcor-som
- dh,stm32mp157c-dhcom-som
- enum:
- st,stm32mp153
- st,stm32mp157
- items:
- enum:
- st,stm32f429i-disco
@@ -39,8 +53,6 @@ properties:
- const: st,stm32h743
- items:
- enum:
- arrow,stm32mp157a-avenger96 # Avenger96
- lxa,stm32mp157c-mc1
- shiratech,stm32mp157a-iot-box # IoT Box
- shiratech,stm32mp157a-stinger96 # Stinger96
- st,stm32mp157c-ed1
@@ -52,6 +64,13 @@ properties:
- const: st,stm32mp157c-ev1
- const: st,stm32mp157c-ed1
- const: st,stm32mp157
- description: Octavo OSD32MP15x System-in-Package based boards
items:
- enum:
- lxa,stm32mp157c-mc1 # Linux Automation MC-1
- const: oct,stm32mp15xx-osd32
- enum:
- st,stm32mp157
- description: Odyssey STM32MP1 SoM based Boards
items:
- enum:

23
Documentation/devicetree/bindings/arm/sunxi.yaml
View File

@@ -201,6 +201,19 @@ properties:
- const: dserve,dsrv9703c
- const: allwinner,sun4i-a10
- description: Elimo Engineering Impetus SoM
items:
- const: elimo,impetus
- const: sochip,s3
- const: allwinner,sun8i-v3
- description: Elimo Engineering Initium
items:
- const: elimo,initium
- const: elimo,impetus
- const: sochip,s3
- const: allwinner,sun8i-v3
- description: Empire Electronix D709 Tablet
items:
- const: empire-electronix,d709
@@ -251,6 +264,16 @@ properties:
- const: friendlyarm,nanopi-neo-plus2
- const: allwinner,sun50i-h5
- description: FriendlyARM NanoPi R1
items:
- const: friendlyarm,nanopi-r1
- const: allwinner,sun8i-h3
- description: FriendlyARM ZeroPi
items:
- const: friendlyarm,zeropi
- const: allwinner,sun8i-h3
- description: Gemei G9 Tablet
items:
- const: gemei,g9

3
Documentation/devicetree/bindings/arm/tegra.yaml
View File

@@ -71,6 +71,9 @@ properties:
- const: asus,tilapia
- const: asus,grouper
- const: nvidia,tegra30
- items:
- const: ouya,ouya
- const: nvidia,tegra30
- items:
- enum:
- nvidia,dalmore

3
Documentation/devicetree/bindings/arm/vt8500.yaml
View File

@@ -21,6 +21,5 @@ properties:
- wm,wm8650
- wm,wm8750
- wm,wm8850
additionalProperties: true
additionalProperties: true

44
Documentation/devicetree/bindings/bus/nvidia,tegra210-aconnect.txt
View File

@@ -1,44 +0,0 @@
NVIDIA Tegra ACONNECT Bus
The Tegra ACONNECT bus is an AXI switch which is used to connnect various
components inside the Audio Processing Engine (APE). All CPU accesses to
the APE subsystem go through the ACONNECT via an APB to AXI wrapper.
Required properties:
- compatible: Must be "nvidia,tegra210-aconnect".
- clocks: Must contain the entries for the APE clock (TEGRA210_CLK_APE),
and APE interface clock (TEGRA210_CLK_APB2APE).
- clock-names: Must contain the names "ape" and "apb2ape" for the corresponding
'clocks' entries.
- power-domains: Must contain a phandle that points to the audio powergate
(namely 'aud') for Tegra210.
- #address-cells: The number of cells used to represent physical base addresses
in the aconnect address space. Should be 1.
- #size-cells: The number of cells used to represent the size of an address
range in the aconnect address space. Should be 1.
- ranges: Mapping of the aconnect address space to the CPU address space.
All devices accessed via the ACONNNECT are described by child-nodes.
Example:
aconnect@702c0000 {
compatible = "nvidia,tegra210-aconnect";
clocks = <&tegra_car TEGRA210_CLK_APE>,
<&tegra_car TEGRA210_CLK_APB2APE>;
clock-names = "ape", "apb2ape";
power-domains = <&pd_audio>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x702c0000 0x0 0x702c0000 0x00040000>;
child1 {
...
};
child2 {
...
};
};

82
Documentation/devicetree/bindings/bus/nvidia,tegra210-aconnect.yaml Normal file
View File

@@ -0,0 +1,82 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/bus/nvidia,tegra210-aconnect.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: NVIDIA Tegra ACONNECT Bus
description: |
The Tegra ACONNECT bus is an AXI switch which is used to connnect various
components inside the Audio Processing Engine (APE). All CPU accesses to
the APE subsystem go through the ACONNECT via an APB to AXI wrapper. All
devices accessed via the ACONNNECT are described by child-nodes.
maintainers:
- Jon Hunter <jonathanh@nvidia.com>
properties:
compatible:
oneOf:
- const: nvidia,tegra210-aconnect
- items:
- enum:
- nvidia,tegra186-aconnect
- nvidia,tegra194-aconnect
- const: nvidia,tegra210-aconnect
clocks:
items:
- description: Must contain the entry for APE clock
- description: Must contain the entry for APE interface clock
clock-names:
items:
- const: ape
- const: apb2ape
power-domains:
maxItems: 1
"#address-cells":
const: 1
"#size-cells":
const: 1
ranges: true
patternProperties:
"@[0-9a-f]+$":
type: object
required:
- compatible
- clocks
- clock-names
- power-domains
- "#address-cells"
- "#size-cells"
- ranges
additionalProperties: false
examples:
- |
#include<dt-bindings/clock/tegra210-car.h>
aconnect@702c0000 {
compatible = "nvidia,tegra210-aconnect";
clocks = <&tegra_car TEGRA210_CLK_APE>,
<&tegra_car TEGRA210_CLK_APB2APE>;
clock-names = "ape", "apb2ape";
power-domains = <&pd_audio>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x702c0000 0x702c0000 0x00040000>;
// Child device nodes follow ...
};
...

79
Documentation/devicetree/bindings/clock/imx8qxp-lpcg.yaml
View File

@@ -21,27 +21,58 @@ description: |
The clock consumer should specify the desired clock by having the clock
ID in its "clocks" phandle cell. See the full list of clock IDs from:
include/dt-bindings/clock/imx8-clock.h
include/dt-bindings/clock/imx8-lpcg.h
properties:
compatible:
enum:
- fsl,imx8qxp-lpcg-adma
- fsl,imx8qxp-lpcg-conn
- fsl,imx8qxp-lpcg-dc
- fsl,imx8qxp-lpcg-dsp
- fsl,imx8qxp-lpcg-gpu
- fsl,imx8qxp-lpcg-hsio
- fsl,imx8qxp-lpcg-img
- fsl,imx8qxp-lpcg-lsio
- fsl,imx8qxp-lpcg-vpu
oneOf:
- const: fsl,imx8qxp-lpcg
- items:
- enum:
- fsl,imx8qm-lpcg
- const: fsl,imx8qxp-lpcg
- enum:
- fsl,imx8qxp-lpcg-adma
- fsl,imx8qxp-lpcg-conn
- fsl,imx8qxp-lpcg-dc
- fsl,imx8qxp-lpcg-dsp
- fsl,imx8qxp-lpcg-gpu
- fsl,imx8qxp-lpcg-hsio
- fsl,imx8qxp-lpcg-img
- fsl,imx8qxp-lpcg-lsio
- fsl,imx8qxp-lpcg-vpu
deprecated: true
reg:
maxItems: 1
'#clock-cells':
const: 1
clocks:
description: |
Input parent clocks phandle array for each clock
minItems: 1
maxItems: 8
clock-indices:
description: |
An integer array indicating the bit offset for each clock.
Refer to <include/dt-bindings/clock/imx8-lpcg.h> for the
supported LPCG clock indices.
minItems: 1
maxItems: 8
clock-output-names:
description: |
Shall be the corresponding names of the outputs.
NOTE this property must be specified in the same order
as the clock-indices property.
minItems: 1
maxItems: 8
power-domains:
maxItems: 1
required:
- compatible
- reg
@@ -51,23 +82,33 @@ additionalProperties: false
examples:
- |
#include <dt-bindings/clock/imx8-clock.h>
#include <dt-bindings/clock/imx8-lpcg.h>
#include <dt-bindings/firmware/imx/rsrc.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
clock-controller@5b200000 {
compatible = "fsl,imx8qxp-lpcg-conn";
reg = <0x5b200000 0xb0000>;
sdhc0_lpcg: clock-controller@5b200000 {
compatible = "fsl,imx8qxp-lpcg";
reg = <0x5b200000 0x10000>;
#clock-cells = <1>;
clocks = <&sdhc0_clk IMX_SC_PM_CLK_PER>,
<&conn_ipg_clk>,
<&conn_axi_clk>;
clock-indices = <IMX_LPCG_CLK_0>,
<IMX_LPCG_CLK_4>,
<IMX_LPCG_CLK_5>;
clock-output-names = "sdhc0_lpcg_per_clk",
"sdhc0_lpcg_ipg_clk",
"sdhc0_lpcg_ahb_clk";
power-domains = <&pd IMX_SC_R_SDHC_0>;
};
mmc@5b010000 {
compatible = "fsl,imx8qxp-usdhc", "fsl,imx7d-usdhc";
interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x5b010000 0x10000>;
clocks = <&conn_lpcg IMX_CONN_LPCG_SDHC0_IPG_CLK>,
<&conn_lpcg IMX_CONN_LPCG_SDHC0_PER_CLK>,
<&conn_lpcg IMX_CONN_LPCG_SDHC0_HCLK>;
clocks = <&sdhc0_lpcg IMX_LPCG_CLK_4>,
<&sdhc0_lpcg IMX_LPCG_CLK_0>,
<&sdhc0_lpcg IMX_LPCG_CLK_5>;
clock-names = "ipg", "per", "ahb";
power-domains = <&pd IMX_SC_R_SDHC_0>;
};

24
Documentation/devicetree/bindings/connector/usb-connector.yaml
View File

@@ -93,6 +93,24 @@ properties:
- device
- dual
typec-power-opmode:
description: Determines the power operation mode that the Type C connector
will support and will advertise through CC pins when it has no power
delivery support.
- "default" corresponds to default USB voltage and current defined by the
USB 2.0 and USB 3.2 specifications, 5V 500mA for USB 2.0 ports and
5V 900mA or 1500mA for USB 3.2 ports in single-lane or dual-lane
operation respectively.
- "1.5A" and "3.0A", 5V 1.5A and 5V 3.0A respectively, as defined in USB
Type-C Cable and Connector specification, when Power Delivery is not
supported.
allOf:
- $ref: /schemas/types.yaml#definitions/string
enum:
- default
- 1.5A
- 3.0A
# The following are optional properties for "usb-c-connector" with power
# delivery support.
source-pdos:
@@ -192,6 +210,12 @@ allOf:
type:
const: micro
anyOf:
- not:
required:
- typec-power-opmode
- new-source-frs-typec-current
additionalProperties: true
examples:

21
Documentation/devicetree/bindings/crypto/picochip-spacc.txt
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@@ -1,21 +0,0 @@
Picochip picoXcell SPAcc (Security Protocol Accelerator) bindings
Picochip picoXcell devices contain crypto offload engines that may be used for
IPSEC and femtocell layer 2 ciphering.
Required properties:
- compatible : "picochip,spacc-ipsec" for the IPSEC offload engine
"picochip,spacc-l2" for the femtocell layer 2 ciphering engine.
- reg : Offset and length of the register set for this device
- interrupts : The interrupt line from the SPAcc.
- ref-clock : The input clock that drives the SPAcc.
Example SPAcc node:
spacc@10000 {
compatible = "picochip,spacc-ipsec";
reg = <0x100000 0x10000>;
interrupt-parent = <&vic0>;
interrupts = <24>;
ref-clock = <&ipsec_clk>, "ref";
};

2
Documentation/devicetree/bindings/display/imx/fsl-imx-drm.txt
View File

@@ -12,7 +12,7 @@ Required properties:
example:
display-subsystem {
compatible = "fsl,display-subsystem";
compatible = "fsl,imx-display-subsystem";
ports = <&ipu_di0>;
};

56
Documentation/devicetree/bindings/dma/nvidia,tegra210-adma.txt
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@@ -1,56 +0,0 @@
* NVIDIA Tegra Audio DMA (ADMA) controller
The Tegra Audio DMA controller that is used for transferring data
between system memory and the Audio Processing Engine (APE).
Required properties:
- compatible: Should contain one of the following:
- "nvidia,tegra210-adma": for Tegra210
- "nvidia,tegra186-adma": for Tegra186 and Tegra194
- reg: Should contain DMA registers location and length. This should be
a single entry that includes all of the per-channel registers in one
contiguous bank.
- interrupts: Should contain all of the per-channel DMA interrupts in
ascending order with respect to the DMA channel index.
- clocks: Must contain one entry for the ADMA module clock
(TEGRA210_CLK_D_AUDIO).
- clock-names: Must contain the name "d_audio" for the corresponding
'clocks' entry.
- #dma-cells : Must be 1. The first cell denotes the receive/transmit
request number and should be between 1 and the maximum number of
requests supported. This value corresponds to the RX/TX_REQUEST_SELECT
fields in the ADMA_CHn_CTRL register.
Example:
adma: dma@702e2000 {
compatible = "nvidia,tegra210-adma";
reg = <0x0 0x702e2000 0x0 0x2000>;
interrupt-parent = <&tegra_agic>;
interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car TEGRA210_CLK_D_AUDIO>;
clock-names = "d_audio";
#dma-cells = <1>;
};

99
Documentation/devicetree/bindings/dma/nvidia,tegra210-adma.yaml Normal file
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@@ -0,0 +1,99 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/dma/nvidia,tegra210-adma.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: NVIDIA Tegra Audio DMA (ADMA) controller
description: |
The Tegra Audio DMA controller is used for transferring data
between system memory and the Audio Processing Engine (APE).
maintainers:
- Jon Hunter <jonathanh@nvidia.com>
allOf:
- $ref: "dma-controller.yaml#"
properties:
compatible:
oneOf:
- enum:
- nvidia,tegra210-adma
- nvidia,tegra186-adma
- items:
- const: nvidia,tegra194-adma
- const: nvidia,tegra186-adma
reg:
maxItems: 1
interrupts:
description: |
Should contain all of the per-channel DMA interrupts in
ascending order with respect to the DMA channel index.
minItems: 1
maxItems: 32
clocks:
description: Must contain one entry for the ADMA module clock
maxItems: 1
clock-names:
const: d_audio
"#dma-cells":
description: |
The first cell denotes the receive/transmit request number and
should be between 1 and the maximum number of requests supported.
This value corresponds to the RX/TX_REQUEST_SELECT fields in the
ADMA_CHn_CTRL register.
const: 1
required:
- compatible
- reg
- interrupts
- clocks
- clock-names
additionalProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include<dt-bindings/clock/tegra210-car.h>
dma-controller@702e2000 {
compatible = "nvidia,tegra210-adma";
reg = <0x702e2000 0x2000>;
interrupt-parent = <&tegra_agic>;
interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car TEGRA210_CLK_D_AUDIO>;
clock-names = "d_audio";
#dma-cells = <1>;
};
...

17
Documentation/devicetree/bindings/gpu/arm,mali-bifrost.yaml
View File

@@ -52,6 +52,23 @@ properties:
"#cooling-cells":
const: 2
dynamic-power-coefficient:
$ref: '/schemas/types.yaml#/definitions/uint32'
description:
A u32 value that represents the running time dynamic
power coefficient in units of uW/MHz/V^2. The
coefficient can either be calculated from power
measurements or derived by analysis.
The dynamic power consumption of the GPU is
proportional to the square of the Voltage (V) and
the clock frequency (f). The coefficient is used to
calculate the dynamic power as below -
Pdyn = dynamic-power-coefficient * V^2 * f
where voltage is in V, frequency is in MHz.
required:
- compatible
- reg

17
Documentation/devicetree/bindings/gpu/arm,mali-midgard.yaml
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@@ -90,6 +90,23 @@ properties:
dma-coherent: true
dynamic-power-coefficient:
$ref: '/schemas/types.yaml#/definitions/uint32'
description:
A u32 value that represents the running time dynamic
power coefficient in units of uW/MHz/V^2. The
coefficient can either be calculated from power
measurements or derived by analysis.
The dynamic power consumption of the GPU is
proportional to the square of the Voltage (V) and
the clock frequency (f). The coefficient is used to
calculate the dynamic power as below -
Pdyn = dynamic-power-coefficient * V^2 * f
where voltage is in V, frequency is in MHz.
required:
- compatible
- reg

4
Documentation/devicetree/bindings/gpu/nvidia,gk20a.txt
View File

@@ -97,8 +97,8 @@ Example for GV11B:
gpu@17000000 {
compatible = "nvidia,gv11b";
reg = <0x17000000 0x10000000>,
<0x18000000 0x10000000>;
reg = <0x17000000 0x1000000>,
<0x18000000 0x1000000>;
interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "stall", "nonstall";

41
Documentation/devicetree/bindings/i2c/i2c-gate.txt
View File

@@ -1,41 +0,0 @@
An i2c gate is useful to e.g. reduce the digital noise for RF tuners connected
to the i2c bus. Gates are similar to arbitrators in that you need to perform
some kind of operation to access the i2c bus past the arbitrator/gate, but
there are no competing masters to consider for gates and therefore there is
no arbitration happening for gates.
Common i2c gate properties.
- i2c-gate child node
Required properties for the i2c-gate child node:
- #address-cells = <1>;
- #size-cells = <0>;
Optional properties for i2c-gate child node:
- Child nodes conforming to i2c bus binding
Example :
/*
An Invensense mpu9150 at address 0x68 featuring an on-chip Asahi
Kasei ak8975 compass behind a gate.
*/
mpu9150@68 {
compatible = "invensense,mpu9150";
reg = <0x68>;
interrupt-parent = <&gpio1>;
interrupts = <18 1>;
i2c-gate {
#address-cells = <1>;
#size-cells = <0>;
ax8975@c {
compatible = "ak,ak8975";
reg = <0x0c>;
};
};
};

39
Documentation/devicetree/bindings/i2c/i2c-gate.yaml Normal file
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@@ -0,0 +1,39 @@
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/i2c/i2c-gate.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Common i2c gate properties
maintainers:
- Peter Rosin <peda@axentia.se>
description: |
An i2c gate is useful to e.g. reduce the digital noise for RF tuners connected
to the i2c bus. Gates are similar to arbitrators in that you need to perform
some kind of operation to access the i2c bus past the arbitrator/gate, but
there are no competing masters to consider for gates and therefore there is
no arbitration happening for gates.
allOf:
- $ref: /schemas/i2c/i2c-controller.yaml
properties:
$nodename:
const: i2c-gate
additionalProperties: true
examples:
- |
i2c-gate {
#address-cells = <1>;
#size-cells = <0>;
ak8975@c {
compatible = "ak,ak8975";
reg = <0x0c>;
};
};
...

8
Documentation/devicetree/bindings/i2c/snps,designware-i2c.yaml
View File

@@ -101,8 +101,6 @@ unevaluatedProperties: false
required:
- compatible
- reg
- "#address-cells"
- "#size-cells"
- interrupts
examples:
@@ -110,8 +108,6 @@ examples:
i2c@f0000 {
compatible = "snps,designware-i2c";
reg = <0xf0000 0x1000>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <11>;
clock-frequency = <400000>;
};
@@ -119,8 +115,6 @@ examples:
i2c@1120000 {
compatible = "snps,designware-i2c";
reg = <0x1120000 0x1000>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <12 1>;
clock-frequency = <400000>;
i2c-sda-hold-time-ns = <300>;
@@ -148,8 +142,6 @@ examples:
reg = <0x100400 0x100>, <0x198 0x8>;
pinctrl-0 = <&i2c_pins>;
pinctrl-names = "default";
#address-cells = <1>;
#size-cells = <0>;
interrupts = <8>;
clocks = <&ahb_clk>;
};

9
Documentation/devicetree/bindings/interrupt-controller/arm,gic.yaml
View File

@@ -35,7 +35,6 @@ properties:
- arm,gic-400
- arm,pl390
- arm,tc11mp-gic
- nvidia,tegra210-agic
- qcom,msm-8660-qgic
- qcom,msm-qgic2
@@ -53,6 +52,14 @@ properties:
- const: brcm,brahma-b15-gic
- const: arm,cortex-a15-gic
- oneOf:
- const: nvidia,tegra210-agic
- items:
- enum:
- nvidia,tegra186-agic
- nvidia,tegra194-agic
- const: nvidia,tegra210-agic
interrupt-controller: true
"#address-cells":

6
Documentation/devicetree/bindings/mfd/st,stm32-timers.yaml
View File

@@ -131,7 +131,7 @@ additionalProperties: false
examples:
- |
#include <dt-bindings/clock/stm32mp1-clks.h>
timers2: timers@40000000 {
timers2: timer@40000000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "st,stm32-timers";
@@ -149,9 +149,9 @@ examples:
#pwm-cells = <3>;
st,breakinput = <0 1 5>;
};
timer@0 {
timer@1 {
compatible = "st,stm32-timer-trigger";
reg = <0>;
reg = <1>;
};
counter {
compatible = "st,stm32-timer-counter";

11
Documentation/devicetree/bindings/misc/fsl,dpaa2-console.txt
View File

@@ -1,11 +0,0 @@
DPAA2 console support
Required properties:
- compatible
Value type: <string>
Definition: Must be "fsl,dpaa2-console".
- reg
Value type: <prop-encoded-array>
Definition: A standard property. Specifies the region where the MCFBA
(MC firmware base address) register can be found.

25
Documentation/devicetree/bindings/misc/fsl,dpaa2-console.yaml Normal file
View File

@@ -0,0 +1,25 @@
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
# Copyright 2020 NXP
%YAML 1.2
---
$id: http://devicetree.org/schemas/misc/fsl,dpaa2-console.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: DPAA2 console support
maintainers:
- Laurentiu Tudor <laurentiu.tudor@nxp.com>
properties:
compatible:
const: "fsl,dpaa2-console"
reg:
description: A standard property. Specifies the region where the MCFBA
(MC firmware base address) register can be found.
required:
- compatible
- reg
additionalProperties: false

131
Documentation/devicetree/bindings/mtd/partition.txt
View File

@@ -24,137 +24,10 @@ another partitioning method.
Available bindings are listed in the "partitions" subdirectory.
Fixed Partitions
================
Partitions can be represented by sub-nodes of a flash device. This can be used
on platforms which have strong conventions about which portions of a flash are
used for what purposes, but which don't use an on-flash partition table such
as RedBoot.
The partition table should be a subnode of the flash node and should be named
'partitions'. This node should have the following property:
- compatible : (required) must be "fixed-partitions"
Partitions are then defined in subnodes of the partitions node.
Deprecated: partitions defined in flash node
============================================
For backwards compatibility partitions as direct subnodes of the flash device are
supported. This use is discouraged.
NOTE: also for backwards compatibility, direct subnodes that have a compatible
string are not considered partitions, as they may be used for other bindings.
#address-cells & #size-cells must both be present in the partitions subnode of the
flash device. There are two valid values for both:
<1>: for partitions that require a single 32-bit cell to represent their
size/address (aka the value is below 4 GiB)
<2>: for partitions that require two 32-bit cells to represent their
size/address (aka the value is 4 GiB or greater).
Required properties:
- reg : The partition's offset and size within the flash
Optional properties:
- label : The label / name for this partition. If omitted, the label is taken
from the node name (excluding the unit address).
- read-only : This parameter, if present, is a hint to Linux that this
partition should only be mounted read-only. This is usually used for flash
partitions containing early-boot firmware images or data which should not be
clobbered.
- lock : Do not unlock the partition at initialization time (not supported on
all devices)
- slc-mode: This parameter, if present, allows one to emulate SLC mode on a
partition attached to an MLC NAND thus making this partition immune to
paired-pages corruptions
Examples:
flash@0 {
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "u-boot";
reg = <0x0000000 0x100000>;
read-only;
};
uimage@100000 {
reg = <0x0100000 0x200000>;
};
};
};
flash@1 {
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <2>;
/* a 4 GiB partition */
partition@0 {
label = "filesystem";
reg = <0x00000000 0x1 0x00000000>;
};
};
};
flash@2 {
partitions {
compatible = "fixed-partitions";
#address-cells = <2>;
#size-cells = <2>;
/* an 8 GiB partition */
partition@0 {
label = "filesystem #1";
reg = <0x0 0x00000000 0x2 0x00000000>;
};
/* a 4 GiB partition */
partition@200000000 {
label = "filesystem #2";
reg = <0x2 0x00000000 0x1 0x00000000>;
};
};
};
flash@3 {
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "bootloader";
reg = <0x000000 0x100000>;
read-only;
};
firmware@100000 {
label = "firmware";
reg = <0x100000 0xe00000>;
compatible = "brcm,trx";
};
calibration@f00000 {
label = "calibration";
reg = <0xf00000 0x100000>;
compatible = "fixed-partitions";
ranges = <0 0xf00000 0x100000>;
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "wifi0";
reg = <0x000000 0x080000>;
};
partition@80000 {
label = "wifi1";
reg = <0x080000 0x080000>;
};
};
};
};

152
Documentation/devicetree/bindings/mtd/partitions/fixed-partitions.yaml Normal file
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@@ -0,0 +1,152 @@
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/mtd/partitions/fixed-partitions.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Fixed partitions
description: |
This binding can be used on platforms which have strong conventions about
which portions of a flash are used for what purposes, but which don't use an
on-flash partition table such as RedBoot.
The partition table should be a node named "partitions". Partitions are then
defined as subnodes.
maintainers:
- Rafał Miłecki <rafal@milecki.pl>
properties:
compatible:
const: fixed-partitions
"#address-cells": true
"#size-cells": true
patternProperties:
"@[0-9a-f]+$":
description: node describing a single flash partition
type: object
properties:
reg:
description: partition's offset and size within the flash
maxItems: 1
label:
description: The label / name for this partition. If omitted, the label
is taken from the node name (excluding the unit address).
read-only:
description: This parameter, if present, is a hint that this partition
should only be mounted read-only. This is usually used for flash
partitions containing early-boot firmware images or data which should
not be clobbered.
type: boolean
lock:
description: Do not unlock the partition at initialization time (not
supported on all devices)
type: boolean
slc-mode:
description: This parameter, if present, allows one to emulate SLC mode
on a partition attached to an MLC NAND thus making this partition
immune to paired-pages corruptions
type: boolean
required:
- reg
required:
- "#address-cells"
- "#size-cells"
additionalProperties: true
examples:
- |
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "u-boot";
reg = <0x0000000 0x100000>;
read-only;
};
uimage@100000 {
reg = <0x0100000 0x200000>;
};
};
- |
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <2>;
/* a 4 GiB partition */
partition@0 {
label = "filesystem";
reg = <0x00000000 0x1 0x00000000>;
};
};
- |
partitions {
compatible = "fixed-partitions";
#address-cells = <2>;
#size-cells = <2>;
/* an 8 GiB partition */
partition@0 {
label = "filesystem #1";
reg = <0x0 0x00000000 0x2 0x00000000>;
};
/* a 4 GiB partition */
partition@200000000 {
label = "filesystem #2";
reg = <0x2 0x00000000 0x1 0x00000000>;
};
};
- |
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "bootloader";
reg = <0x000000 0x100000>;
read-only;
};
firmware@100000 {
compatible = "brcm,trx";
label = "firmware";
reg = <0x100000 0xe00000>;
};
calibration@f00000 {
compatible = "fixed-partitions";
label = "calibration";
reg = <0xf00000 0x100000>;
ranges = <0 0xf00000 0x100000>;
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "wifi0";
reg = <0x000000 0x080000>;
};
partition@80000 {
label = "wifi1";
reg = <0x080000 0x080000>;
};
};
};

149
Documentation/devicetree/bindings/net/dsa/b53.txt
View File

@@ -1,149 +0,0 @@
Broadcom BCM53xx Ethernet switches
==================================
Required properties:
- compatible: For external switch chips, compatible string must be exactly one
of: "brcm,bcm5325"
"brcm,bcm53115"
"brcm,bcm53125"
"brcm,bcm53128"
"brcm,bcm5365"
"brcm,bcm5395"
"brcm,bcm5389"
"brcm,bcm5397"
"brcm,bcm5398"
For the BCM11360 SoC, must be:
"brcm,bcm11360-srab" and the mandatory "brcm,cygnus-srab" string
For the BCM5310x SoCs with an integrated switch, must be one of:
"brcm,bcm53010-srab"
"brcm,bcm53011-srab"
"brcm,bcm53012-srab"
"brcm,bcm53018-srab"
"brcm,bcm53019-srab" and the mandatory "brcm,bcm5301x-srab" string
For the BCM5831X/BCM1140x SoCs with an integrated switch, must be one of:
"brcm,bcm11404-srab"
"brcm,bcm11407-srab"
"brcm,bcm11409-srab"
"brcm,bcm58310-srab"
"brcm,bcm58311-srab"
"brcm,bcm58313-srab" and the mandatory "brcm,omega-srab" string
For the BCM585xx/586XX/88312 SoCs with an integrated switch, must be one of:
"brcm,bcm58522-srab"
"brcm,bcm58523-srab"
"brcm,bcm58525-srab"
"brcm,bcm58622-srab"
"brcm,bcm58623-srab"
"brcm,bcm58625-srab"
"brcm,bcm88312-srab" and the mandatory "brcm,nsp-srab string
For the BCM63xx/33xx SoCs with an integrated switch, must be one of:
"brcm,bcm3384-switch"
"brcm,bcm6328-switch"
"brcm,bcm6368-switch" and the mandatory "brcm,bcm63xx-switch"
Required properties for BCM585xx/586xx/88312 SoCs:
- reg: a total of 3 register base addresses, the first one must be the
Switch Register Access block base, the second is the port 5/4 mux
configuration register and the third one is the SGMII configuration
and status register base address.
- interrupts: a total of 13 interrupts must be specified, in the following
order: port 0-5, 7-8 link status change, then the integrated PHY interrupt,
then the timestamping interrupt and the sleep timer interrupts for ports
5,7,8.
Optional properties for BCM585xx/586xx/88312 SoCs:
- reg-names: a total of 3 names matching the 3 base register address, must
be in the following order:
"srab"
"mux_config"
"sgmii_config"
- interrupt-names: a total of 13 names matching the 13 interrupts specified
must be in the following order:
"link_state_p0"
"link_state_p1"
"link_state_p2"
"link_state_p3"
"link_state_p4"
"link_state_p5"
"link_state_p7"
"link_state_p8"
"phy"
"ts"
"imp_sleep_timer_p5"
"imp_sleep_timer_p7"
"imp_sleep_timer_p8"
See Documentation/devicetree/bindings/net/dsa/dsa.txt for a list of additional
required and optional properties.
Examples:
Ethernet switch connected via MDIO to the host, CPU port wired to eth0:
eth0: ethernet@10001000 {
compatible = "brcm,unimac";
reg = <0x10001000 0x1000>;
fixed-link {
speed = <1000>;
full-duplex;
};
};
mdio0: mdio@10000000 {
compatible = "brcm,unimac-mdio";
#address-cells = <1>;
#size-cells = <0>;
switch0: ethernet-switch@1e {
compatible = "brcm,bcm53125";
reg = <30>;
#address-cells = <1>;
#size-cells = <0>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port0@0 {
reg = <0>;
label = "lan1";
};
port1@1 {
reg = <1>;
label = "lan2";
};
port5@5 {
reg = <5>;
label = "cable-modem";
fixed-link {
speed = <1000>;
full-duplex;
};
phy-mode = "rgmii-txid";
};
port8@8 {
reg = <8>;
label = "cpu";
fixed-link {
speed = <1000>;
full-duplex;
};
phy-mode = "rgmii-txid";
ethernet = <&eth0>;
};
};
};
};

249
Documentation/devicetree/bindings/net/dsa/brcm,b53.yaml Normal file
View File

@@ -0,0 +1,249 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/net/dsa/brcm,b53.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Broadcom BCM53xx Ethernet switches
allOf:
- $ref: dsa.yaml#
maintainers:
- Florian Fainelli <f.fainelli@gmail.com>
description:
Broadcom BCM53xx Ethernet switches
properties:
compatible:
oneOf:
- const: brcm,bcm5325
- const: brcm,bcm53115
- const: brcm,bcm53125
- const: brcm,bcm53128
- const: brcm,bcm5365
- const: brcm,bcm5395
- const: brcm,bcm5389
- const: brcm,bcm5397
- const: brcm,bcm5398
- items:
- const: brcm,bcm11360-srab
- const: brcm,cygnus-srab
- items:
- enum:
- brcm,bcm53010-srab
- brcm,bcm53011-srab
- brcm,bcm53012-srab
- brcm,bcm53018-srab
- brcm,bcm53019-srab
- const: brcm,bcm5301x-srab
- items:
- enum:
- brcm,bcm11404-srab
- brcm,bcm11407-srab
- brcm,bcm11409-srab
- brcm,bcm58310-srab
- brcm,bcm58311-srab
- brcm,bcm58313-srab
- const: brcm,omega-srab
- items:
- enum:
- brcm,bcm58522-srab
- brcm,bcm58523-srab
- brcm,bcm58525-srab
- brcm,bcm58622-srab
- brcm,bcm58623-srab
- brcm,bcm58625-srab
- brcm,bcm88312-srab
- const: brcm,nsp-srab
- items:
- enum:
- brcm,bcm3384-switch
- brcm,bcm6328-switch
- brcm,bcm6368-switch
- const: brcm,bcm63xx-switch
required:
- compatible
- reg
# BCM585xx/586xx/88312 SoCs
if:
properties:
compatible:
contains:
enum:
- brcm,bcm58522-srab
- brcm,bcm58523-srab
- brcm,bcm58525-srab
- brcm,bcm58622-srab
- brcm,bcm58623-srab
- brcm,bcm58625-srab
- brcm,bcm88312-srab
then:
properties:
reg:
minItems: 3
maxItems: 3
reg-names:
items:
- const: srab
- const: mux_config
- const: sgmii_config
interrupts:
minItems: 13
maxItems: 13
interrupt-names:
items:
- const: link_state_p0
- const: link_state_p1
- const: link_state_p2
- const: link_state_p3
- const: link_state_p4
- const: link_state_p5
- const: link_state_p7
- const: link_state_p8
- const: phy
- const: ts
- const: imp_sleep_timer_p5
- const: imp_sleep_timer_p7
- const: imp_sleep_timer_p8
required:
- interrupts
else:
properties:
reg:
maxItems: 1
unevaluatedProperties: false
examples:
- |
mdio {
#address-cells = <1>;
#size-cells = <0>;
ethernet-switch@1e {
compatible = "brcm,bcm53125";
reg = <30>;
ethernet-ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
label = "lan1";
};
port@1 {
reg = <1>;
label = "lan2";
};
port@5 {
reg = <5>;
label = "cable-modem";
phy-mode = "rgmii-txid";
fixed-link {
speed = <1000>;
full-duplex;
};
};
port@8 {
reg = <8>;
label = "cpu";
phy-mode = "rgmii-txid";
ethernet = <&eth0>;
fixed-link {
speed = <1000>;
full-duplex;
};
};
};
};
};
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
axi {
#address-cells = <1>;
#size-cells = <1>;
switch@36000 {
compatible = "brcm,bcm58623-srab", "brcm,nsp-srab";
reg = <0x36000 0x1000>,
<0x3f308 0x8>,
<0x3f410 0xc>;
reg-names = "srab", "mux_config", "sgmii_config";
interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "link_state_p0",
"link_state_p1",
"link_state_p2",
"link_state_p3",
"link_state_p4",
"link_state_p5",
"link_state_p7",
"link_state_p8",
"phy",
"ts",
"imp_sleep_timer_p5",
"imp_sleep_timer_p7",
"imp_sleep_timer_p8";
ethernet-ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
label = "port0";
reg = <0>;
};
port@1 {
label = "port1";
reg = <1>;
};
port@2 {
label = "port2";
reg = <2>;
};
port@3 {
label = "port3";
reg = <3>;
};
port@4 {
label = "port4";
reg = <4>;
};
port@8 {
ethernet = <&amac2>;
label = "cpu";
reg = <8>;
fixed-link {
speed = <1000>;
full-duplex;
};
};
};
};
};

6
Documentation/devicetree/bindings/net/dsa/dsa.yaml
View File

@@ -20,7 +20,7 @@ select: false
properties:
$nodename:
pattern: "^switch(@.*)?$"
pattern: "^(ethernet-)?switch(@.*)?$"
dsa,member:
minItems: 2
@@ -78,6 +78,10 @@ patternProperties:
mac-address: true
sfp: true
managed: true
required:
- reg

1
Documentation/devicetree/bindings/net/ethernet-controller.yaml
View File

@@ -95,6 +95,7 @@ properties:
# 10GBASE-KR, XFI, SFI
- 10gbase-kr
- usxgmii
- 10gbase-r
phy-mode:
$ref: "#/properties/phy-connection-type"

60
Documentation/devicetree/bindings/net/fsl,qoriq-mc-dpmac.yaml Normal file
View File

@@ -0,0 +1,60 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/net/fsl,qoriq-mc-dpmac.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: DPAA2 MAC bindings
maintainers:
- Ioana Ciornei <ioana.ciornei@nxp.com>
description:
This binding represents the DPAA2 MAC objects found on the fsl-mc bus and
located under the 'dpmacs' node for the fsl-mc bus DTS node.
allOf:
- $ref: "ethernet-controller.yaml#"
properties:
compatible:
const: fsl,qoriq-mc-dpmac
reg:
maxItems: 1
description: The DPMAC number
phy-handle: true
phy-connection-type: true
phy-mode: true
pcs-handle:
$ref: /schemas/types.yaml#definitions/phandle
description:
A reference to a node representing a PCS PHY device found on
the internal MDIO bus.
managed: true
required:
- reg
additionalProperties: false
examples:
- |
dpmacs {
#address-cells = <1>;
#size-cells = <0>;
ethernet@4 {
compatible = "fsl,qoriq-mc-dpmac";
reg = <0x4>;
phy-handle = <&mdio1_phy6>;
phy-connection-type = "qsgmii";
managed = "in-band-status";
pcs-handle = <&pcs3_1>;
};
};

2
Documentation/devicetree/bindings/net/macb.txt
View File

@@ -7,8 +7,6 @@ Required properties:
Use "cdns,sam9x60-macb" for Microchip sam9x60 SoC.
Use "cdns,np4-macb" for NP4 SoC devices.
Use "cdns,at32ap7000-macb" for other 10/100 usage or use the generic form: "cdns,macb".
Use "cdns,pc302-gem" for Picochip picoXcell pc302 and later devices based on
the Cadence GEM, or the generic form: "cdns,gem".
Use "atmel,sama5d2-gem" for the GEM IP (10/100) available on Atmel sama5d2 SoCs.
Use "atmel,sama5d3-macb" for the 10/100Mbit IP available on Atmel sama5d3 SoCs.
Use "atmel,sama5d3-gem" for the Gigabit IP available on Atmel sama5d3 SoCs.

9
Documentation/devicetree/bindings/pci/rcar-pci-ep.yaml
View File

@@ -32,6 +32,10 @@ properties:
- const: memory2
- const: memory3
interrupts:
minItems: 3
maxItems: 3
power-domains:
maxItems: 1
@@ -53,6 +57,7 @@ required:
- compatible
- reg
- reg-names
- interrupts
- resets
- power-domains
- clocks
@@ -64,6 +69,7 @@ additionalProperties: false
examples:
- |
#include <dt-bindings/clock/r8a774c0-cpg-mssr.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/power/r8a774c0-sysc.h>
pcie0_ep: pcie-ep@fe000000 {
@@ -75,6 +81,9 @@ examples:
<0x30000000 0x8000000>,
<0x38000000 0x8000000>;
reg-names = "apb-base", "memory0", "memory1", "memory2", "memory3";
interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
resets = <&cpg 319>;
power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
clocks = <&cpg CPG_MOD 319>;

2
Documentation/devicetree/bindings/pinctrl/nvidia,tegra194-pinmux.txt
View File

@@ -99,7 +99,7 @@ Example:
nvidia,schmitt = <TEGRA_PIN_DISABLE>;
nvidia,lpdr = <TEGRA_PIN_ENABLE>;
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
nvidia,io-high-voltage = <TEGRA_PIN_ENABLE>;
nvidia,io-hv = <TEGRA_PIN_ENABLE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
};

293
Documentation/devicetree/bindings/power/mediatek,power-controller.yaml Normal file
View File

@@ -0,0 +1,293 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/power/mediatek,power-controller.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Mediatek Power Domains Controller
maintainers:
- Weiyi Lu <weiyi.lu@mediatek.com>
- Matthias Brugger <mbrugger@suse.com>
description: |
Mediatek processors include support for multiple power domains which can be
powered up/down by software based on different application scenes to save power.
IP cores belonging to a power domain should contain a 'power-domains'
property that is a phandle for SCPSYS node representing the domain.
properties:
$nodename:
const: power-controller
compatible:
enum:
- mediatek,mt8173-power-controller
- mediatek,mt8183-power-controller
- mediatek,mt8192-power-controller
'#power-domain-cells':
const: 1
'#address-cells':
const: 1
'#size-cells':
const: 0
patternProperties:
"^power-domain@[0-9a-f]+$":
type: object
description: |
Represents the power domains within the power controller node as documented
in Documentation/devicetree/bindings/power/power-domain.yaml.
properties:
'#power-domain-cells':
description:
Must be 0 for nodes representing a single PM domain and 1 for nodes
providing multiple PM domains.
'#address-cells':
const: 1
'#size-cells':
const: 0
reg:
description: |
Power domain index. Valid values are defined in:
"include/dt-bindings/power/mt8173-power.h" - for MT8173 type power domain.
"include/dt-bindings/power/mt8183-power.h" - for MT8183 type power domain.
"include/dt-bindings/power/mt8192-power.h" - for MT8192 type power domain.
maxItems: 1
clocks:
description: |
A number of phandles to clocks that need to be enabled during domain
power-up sequencing.
clock-names:
description: |
List of names of clocks, in order to match the power-up sequencing
for each power domain we need to group the clocks by name. BASIC
clocks need to be enabled before enabling the corresponding power
domain, and should not have a '-' in their name (i.e mm, mfg, venc).
SUSBYS clocks need to be enabled before releasing the bus protection,
and should contain a '-' in their name (i.e mm-0, isp-0, cam-0).
In order to follow properly the power-up sequencing, the clocks must
be specified by order, adding first the BASIC clocks followed by the
SUSBSYS clocks.
mediatek,infracfg:
$ref: /schemas/types.yaml#definitions/phandle
description: phandle to the device containing the INFRACFG register range.
mediatek,smi:
$ref: /schemas/types.yaml#definitions/phandle
description: phandle to the device containing the SMI register range.
patternProperties:
"^power-domain@[0-9a-f]+$":
type: object
description: |
Represents a power domain child within a power domain parent node.
properties:
'#power-domain-cells':
description:
Must be 0 for nodes representing a single PM domain and 1 for nodes
providing multiple PM domains.
'#address-cells':
const: 1
'#size-cells':
const: 0
reg:
maxItems: 1
clocks:
description: |
A number of phandles to clocks that need to be enabled during domain
power-up sequencing.
clock-names:
description: |
List of names of clocks, in order to match the power-up sequencing
for each power domain we need to group the clocks by name. BASIC
clocks need to be enabled before enabling the corresponding power
domain, and should not have a '-' in their name (i.e mm, mfg, venc).
SUSBYS clocks need to be enabled before releasing the bus protection,
and should contain a '-' in their name (i.e mm-0, isp-0, cam-0).
In order to follow properly the power-up sequencing, the clocks must
be specified by order, adding first the BASIC clocks followed by the
SUSBSYS clocks.
mediatek,infracfg:
$ref: /schemas/types.yaml#definitions/phandle
description: phandle to the device containing the INFRACFG register range.
mediatek,smi:
$ref: /schemas/types.yaml#definitions/phandle
description: phandle to the device containing the SMI register range.
patternProperties:
"^power-domain@[0-9a-f]+$":
type: object
description: |
Represents a power domain child within a power domain parent node.
properties:
'#power-domain-cells':
description:
Must be 0 for nodes representing a single PM domain and 1 for nodes
providing multiple PM domains.
'#address-cells':
const: 1
'#size-cells':
const: 0
reg:
maxItems: 1
clocks:
description: |
A number of phandles to clocks that need to be enabled during domain
power-up sequencing.
clock-names:
description: |
List of names of clocks, in order to match the power-up sequencing
for each power domain we need to group the clocks by name. BASIC
clocks need to be enabled before enabling the corresponding power
domain, and should not have a '-' in their name (i.e mm, mfg, venc).
SUSBYS clocks need to be enabled before releasing the bus protection,
and should contain a '-' in their name (i.e mm-0, isp-0, cam-0).
In order to follow properly the power-up sequencing, the clocks must
be specified by order, adding first the BASIC clocks followed by the
SUSBSYS clocks.
mediatek,infracfg:
$ref: /schemas/types.yaml#definitions/phandle
description: phandle to the device containing the INFRACFG register range.
mediatek,smi:
$ref: /schemas/types.yaml#definitions/phandle
description: phandle to the device containing the SMI register range.
required:
- reg
additionalProperties: false
required:
- reg
additionalProperties: false
required:
- reg
additionalProperties: false
required:
- compatible
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/mt8173-clk.h>
#include <dt-bindings/power/mt8173-power.h>
soc {
#address-cells = <2>;
#size-cells = <2>;
scpsys: syscon@10006000 {
compatible = "syscon", "simple-mfd";
reg = <0 0x10006000 0 0x1000>;
spm: power-controller {
compatible = "mediatek,mt8173-power-controller";
#address-cells = <1>;
#size-cells = <0>;
#power-domain-cells = <1>;
/* power domains of the SoC */
power-domain@MT8173_POWER_DOMAIN_VDEC {
reg = <MT8173_POWER_DOMAIN_VDEC>;
clocks = <&topckgen CLK_TOP_MM_SEL>;
clock-names = "mm";
#power-domain-cells = <0>;
};
power-domain@MT8173_POWER_DOMAIN_VENC {
reg = <MT8173_POWER_DOMAIN_VENC>;
clocks = <&topckgen CLK_TOP_MM_SEL>,
<&topckgen CLK_TOP_VENC_SEL>;
clock-names = "mm", "venc";
#power-domain-cells = <0>;
};
power-domain@MT8173_POWER_DOMAIN_ISP {
reg = <MT8173_POWER_DOMAIN_ISP>;
clocks = <&topckgen CLK_TOP_MM_SEL>;
clock-names = "mm";
#power-domain-cells = <0>;
};
power-domain@MT8173_POWER_DOMAIN_MM {
reg = <MT8173_POWER_DOMAIN_MM>;
clocks = <&topckgen CLK_TOP_MM_SEL>;
clock-names = "mm";
#power-domain-cells = <0>;
mediatek,infracfg = <&infracfg>;
};
power-domain@MT8173_POWER_DOMAIN_VENC_LT {
reg = <MT8173_POWER_DOMAIN_VENC_LT>;
clocks = <&topckgen CLK_TOP_MM_SEL>,
<&topckgen CLK_TOP_VENC_LT_SEL>;
clock-names = "mm", "venclt";
#power-domain-cells = <0>;
};
power-domain@MT8173_POWER_DOMAIN_AUDIO {
reg = <MT8173_POWER_DOMAIN_AUDIO>;
#power-domain-cells = <0>;
};
power-domain@MT8173_POWER_DOMAIN_USB {
reg = <MT8173_POWER_DOMAIN_USB>;
#power-domain-cells = <0>;
};
power-domain@MT8173_POWER_DOMAIN_MFG_ASYNC {
reg = <MT8173_POWER_DOMAIN_MFG_ASYNC>;
clocks = <&clk26m>;
clock-names = "mfg";
#address-cells = <1>;
#size-cells = <0>;
#power-domain-cells = <1>;
power-domain@MT8173_POWER_DOMAIN_MFG_2D {
reg = <MT8173_POWER_DOMAIN_MFG_2D>;
#address-cells = <1>;
#size-cells = <0>;
#power-domain-cells = <1>;
power-domain@MT8173_POWER_DOMAIN_MFG {
reg = <MT8173_POWER_DOMAIN_MFG>;
#power-domain-cells = <0>;
mediatek,infracfg = <&infracfg>;
};
};
};
};
};
};

2
Documentation/devicetree/bindings/reset/snps,dw-reset.txt
View File

@@ -23,7 +23,7 @@ example:
#reset-cells = <1>;
};
dw_rst_2: reset-controller@1000 {i
dw_rst_2: reset-controller@1000 {
compatible = "snps,dw-low-reset";
reg = <0x1000 0x8>;
#reset-cells = <1>;

7
Documentation/devicetree/bindings/timer/snps,dw-apb-timer.yaml
View File

@@ -38,13 +38,6 @@ properties:
clock-frequency: true
clock-freq:
$ref: "/schemas/types.yaml#/definitions/uint32"
description: |
Has the same meaning as the 'clock-frequency' property - timer clock
frequency in HZ, but is defined only for the backwards compatibility
with the picoxcell platform.
additionalProperties: false
required:

8
Documentation/devicetree/bindings/trivial-devices.yaml
View File

@@ -30,6 +30,12 @@ properties:
- ad,ad7414
# ADM9240: Complete System Hardware Monitor for uProcessor-Based Systems
- ad,adm9240
# Analog Devices ADP5585 Keypad Decoder and I/O Expansion
- adi,adp5585
# Analog Devices ADP5585 Keypad Decoder and I/O Expansion with support for Row5
- adi,adp5585-02
# Analog Devices ADP5589 Keypad Decoder and I/O Expansion
- adi,adp5589
# +/-1C TDM Extended Temp Range I.C
- adi,adt7461
# +/-1C TDM Extended Temp Range I.C
@@ -62,6 +68,8 @@ properties:
- dallas,ds4510
# Digital Thermometer and Thermostat
- dallas,ds75
# 1/4 Brick DC/DC Regulated Power Module
- delta,q54sj108a2
# Devantech SRF02 ultrasonic ranger in I2C mode
- devantech,srf02
# Devantech SRF08 ultrasonic ranger

87
Documentation/devicetree/bindings/usb/st,stusb160x.yaml Normal file
View File

@@ -0,0 +1,87 @@
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: "http://devicetree.org/schemas/usb/st,stusb160x.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
title: STMicroelectronics STUSB160x Type-C controller bindings
maintainers:
- Amelie Delaunay <amelie.delaunay@st.com>
properties:
compatible:
enum:
- st,stusb1600
reg:
maxItems: 1
interrupts:
maxItems: 1
vdd-supply:
description: main power supply (4.1V-22V)
vsys-supply:
description: low power supply (3.0V-5.5V)
vconn-supply:
description: power supply (2.7V-5.5V) used to supply VConn on CC pin in
source or dual power role
connector:
type: object
allOf:
- $ref: ../connector/usb-connector.yaml
properties:
compatible:
const: usb-c-connector
power-role: true
typec-power-opmode: true
required:
- compatible
required:
- compatible
- reg
- connector
additionalProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/irq.h>
i2c4 {
#address-cells = <1>;
#size-cells = <0>;
typec: stusb1600@28 {
compatible = "st,stusb1600";
reg = <0x28>;
vdd-supply = <&vbus_drd>;
vsys-supply = <&vdd_usb>;
interrupts = <11 IRQ_TYPE_EDGE_FALLING>;
interrupt-parent = <&gpioi>;
typec_con: connector {
compatible = "usb-c-connector";
label = "USB-C";
power-role = "dual";
data-role = "dual";
typec-power-opmode = "default";
port {
typec_con_ep: endpoint {
remote-endpoint = <&usbotg_hs_ep>;
};
};
};
};
};
...

34
Documentation/devicetree/bindings/vendor-prefixes.yaml
View File

@@ -16,7 +16,7 @@ properties: {}
patternProperties:
# Prefixes which are not vendors, but followed the pattern
# DO NOT ADD NEW PROPERTIES TO THIS LIST
"^(at25|devbus|dmacap|dsa|exynos|fsi[ab]|gpio-fan|gpio|gpmc|hdmi|i2c-gpio),.*": true
"^(at25|bm|devbus|dmacap|dsa|exynos|fsi[ab]|gpio-fan|gpio-key|gpio|gpmc|hdmi|i2c-gpio),.*": true
"^(keypad|m25p|max8952|max8997|max8998|mpmc),.*": true
"^(pinctrl-single|#pinctrl-single|PowerPC),.*": true
"^(pl022|pxa-mmc|rcar_sound|rotary-encoder|s5m8767|sdhci),.*": true
@@ -25,6 +25,8 @@ patternProperties:
# Keep list in alphabetical order.
"^70mai,.*":
description: 70mai Co., Ltd.
"^abb,.*":
description: ABB
"^abilis,.*":
description: Abilis Systems
"^abracon,.*":
@@ -67,6 +69,8 @@ patternProperties:
description: AlphaScale Integrated Circuits Systems, Inc.
"^alps,.*":
description: Alps Electric Co., Ltd.
"^alt,.*":
description: Altus-Escon-Company BV
"^altr,.*":
description: Altera Corp.
"^amarula,.*":
@@ -81,6 +85,8 @@ patternProperties:
description: Shenzhen Amediatech Technology Co., Ltd
"^amlogic,.*":
description: Amlogic, Inc.
"^ampere,.*":
description: Ampere Computing LLC
"^ampire,.*":
description: Ampire Co., Ltd.
"^ams,.*":
@@ -317,10 +323,14 @@ patternProperties:
description: Einfochips
"^elan,.*":
description: Elan Microelectronic Corp.
"^element14,.*":
description: Element14 (A Premier Farnell Company)
"^elgin,.*":
description: Elgin S/A.
"^elida,.*":
description: Shenzhen Elida Technology Co., Ltd.
"^elimo,.*":
description: Elimo Engineering Ltd.
"^embest,.*":
description: Shenzhen Embest Technology Co., Ltd.
"^emlid,.*":
@@ -379,6 +389,8 @@ patternProperties:
description: Shenzhen Feixin Photoelectic Co., Ltd
"^feiyang,.*":
description: Shenzhen Fly Young Technology Co.,LTD.
"^fii,.*":
description: Foxconn Industrial Internet
"^firefly,.*":
description: Firefly
"^focaltech,.*":
@@ -455,6 +467,8 @@ patternProperties:
description: Holt Integrated Circuits, Inc.
"^honeywell,.*":
description: Honeywell
"^honestar,.*":
description: Honestar Technologies Co., Ltd.
"^hoperun,.*":
description: Jiangsu HopeRun Software Co., Ltd.
"^hp,.*":
@@ -557,6 +571,8 @@ patternProperties:
description: Kionix, Inc.
"^kobo,.*":
description: Rakuten Kobo Inc.
"^kobol,.*":
description: Kobol Innovations Pte. Ltd.
"^koe,.*":
description: Kaohsiung Opto-Electronics Inc.
"^kontron,.*":
@@ -659,6 +675,8 @@ patternProperties:
description: MEMSIC Inc.
"^menlo,.*":
description: Menlo Systems GmbH
"^mentor,.*":
description: Mentor Graphics
"^meraki,.*":
description: Cisco Meraki, LLC
"^merrii,.*":
@@ -673,6 +691,8 @@ patternProperties:
description: Micron Technology Inc.
"^microsoft,.*":
description: Microsoft Corporation
"^microsys,.*":
description: MicroSys Electronics GmbH
"^mikroe,.*":
description: MikroElektronika d.o.o.
"^mikrotik,.*":
@@ -766,6 +786,8 @@ patternProperties:
description: NXP Semiconductors
"^oceanic,.*":
description: Oceanic Systems (UK) Ltd.
"^oct,.*":
description: Octavo Systems LLC
"^okaya,.*":
description: Okaya Electric America, Inc.
"^oki,.*":
@@ -798,6 +820,8 @@ patternProperties:
description: Ortus Technology Co., Ltd.
"^osddisplays,.*":
description: OSD Displays
"^ouya,.*":
description: Ouya Inc.
"^overkiz,.*":
description: Overkiz SAS
"^ovti,.*":
@@ -900,6 +924,8 @@ patternProperties:
description: iMX6 Rex Project
"^rervision,.*":
description: Shenzhen Rervision Technology Co., Ltd.
"^revotics,.*":
description: Revolution Robotics, Inc. (Revotics)
"^richtek,.*":
description: Richtek Technology Corporation
"^ricoh,.*":
@@ -1105,7 +1131,7 @@ patternProperties:
"^tpo,.*":
description: TPO
"^tq,.*":
description: TQ Systems GmbH
description: TQ-Systems GmbH
"^tronfy,.*":
description: Tronfy
"^tronsmart,.*":
@@ -1148,12 +1174,16 @@ patternProperties:
description: Vamrs Ltd.
"^variscite,.*":
description: Variscite Ltd.
"^vdl,.*":
description: Van der Laan b.v.
"^via,.*":
description: VIA Technologies, Inc.
"^videostrong,.*":
description: Videostrong Technology Co., Ltd.
"^virtio,.*":
description: Virtual I/O Device Specification, developed by the OASIS consortium
"^virtual,.*":
description: Used for virtual device without specific vendor.
"^vishay,.*":
description: Vishay Intertechnology, Inc
"^vitesse,.*":

16
Documentation/devicetree/bindings/watchdog/fsl-imx-wdt.yaml
View File

@@ -18,10 +18,26 @@ properties:
- const: fsl,imx21-wdt
- items:
- enum:
- fsl,imx25-wdt
- fsl,imx27-wdt
- fsl,imx31-wdt
- fsl,imx35-wdt
- fsl,imx50-wdt
- fsl,imx51-wdt
- fsl,imx53-wdt
- fsl,imx6q-wdt
- fsl,imx6sl-wdt
- fsl,imx6sll-wdt
- fsl,imx6sx-wdt
- fsl,imx6ul-wdt
- fsl,imx7d-wdt
- fsl,imx8mm-wdt
- fsl,imx8mn-wdt
- fsl,imx8mp-wdt
- fsl,imx8mq-wdt
- fsl,ls1012a-wdt
- fsl,ls1043a-wdt
- fsl,vf610-wdt
- const: fsl,imx21-wdt
reg:

145
Documentation/hid/amd-sfh-hid.rst Normal file
View File

@@ -0,0 +1,145 @@
.. SPDX-License-Identifier: GPL-2.0
AMD Sensor Fusion Hub
=====================
AMD Sensor Fusion Hub (SFH) is part of an SOC starting from Ryzen based platforms.
The solution is working well on several OEM products. AMD SFH uses HID over PCIe bus.
In terms of architecture it resembles ISH, however the major difference is all
the HID reports are generated as part of the kernel driver.
1. Block Diagram
================
::
---------------------------------
| HID User Space Applications |
- -------------------------------
---------------------------------------------
---------------------------------
| HID Core |
---------------------------------
---------------------------------
| AMD HID Transport |
---------------------------------
--------------------------------
| AMD HID Client |
| with HID Report Generator|
--------------------------------
--------------------------------
| AMD MP2 PCIe Driver |
--------------------------------
OS
---------------------------------------------
Hardware + Firmware
--------------------------------
| SFH MP2 Processor |
--------------------------------
AMD HID Transport Layer
-----------------------
AMD SFH transport is also implemented as a bus. Each client application executing in the AMD MP2 is
registered as a device on this bus. Here: MP2 which is an ARM core connected to x86 for processing
sensor data. The layer, which binds each device (AMD SFH HID driver) identifies the device type and
registers with the hid core. Transport layer attach a constant "struct hid_ll_driver" object with
each device. Once a device is registered with HID core, the callbacks provided via this struct are
used by HID core to communicate with the device. AMD HID Transport layer implements the synchronous calls.
AMD HID Client Layer
--------------------
This layer is responsible to implement HID request and descriptors. As firmware is OS agnostic, HID
client layer fills the HID request structure and descriptors. HID client layer is complex as it is
interface between MP2 PCIe layer and HID. HID client layer initialized the MP2 PCIe layer and holds
the instance of MP2 layer. It identifies the number of sensors connected using MP2-PCIe layer. Base
on that allocates the DRAM address for each and every sensor and pass it to MP2-PCIe driver.On
enumeration of each the sensor, client layer fills the HID Descriptor structure and HID input repor
structure. HID Feature report structure is optional. The report descriptor structure varies from
sensor to sensor.
AMD MP2 PCIe layer
------------------
MP2 PCIe Layer is responsible for making all transactions with the firmware over PCIe.
The connection establishment between firmware and PCIe happens here.
The communication between X86 and MP2 is split into three parts.
1. Command transfer via the C2P mailbox registers.
2. Data transfer via DRAM.
3. Supported sensor info via P2C registers.
Commands are sent to MP2 using C2P Mailbox registers. Writing into C2P Message registers generate
interrupt to MP2. The client layer allocates the physical memory and the same is sent to MP2 via
the PCI layer. MP2 firmware writes the command output to the access DRAM memory which the client
layer has allocated. Firmware always writes minimum of 32 bytes into DRAM. So as a protocol driver
shall allocate minimum of 32 bytes DRAM space.
Enumeration and Probing flow
----------------------------
::
HID AMD AMD AMD -PCIe MP2
Core Transport Client layer layer FW
| | | | |
| | | on Boot Driver Loaded |
| | | | |
| | | MP2-PCIe Int |
| | | | |
| | |---Get Number of sensors-> | |
| | | Read P2C |
| | | Register |
| | | | |
| | | Loop(for No of Sensors) | |
| | |----------------------| | |
| | | Create HID Descriptor| | |
| | | Create Input report | | |
| | | Descriptor Map | | |
| | | the MP2 FW Index to | | |
| | | HID Index | | |
| | | Allocate the DRAM | Enable |
| | | address | Sensors |
| | |----------------------| | |
| | HID transport| | Enable |
| |<--Probe------| |---Sensor CMD--> |
| | Create the | | |
| | HID device | | |
| | (MFD) | | |
| | by Populating| | |
| | the HID | | |
| | ll_driver | | |
| HID | | | |
| add | | | |
|Device | | | |
|<------------- | | | |
Data Flow from Application to the AMD SFH Driver
------------------------------------------------
::
| | | | |
| | | | |
| | | | |
| | | | |
| | | | |
|HID_req | | | |
|get_report | | | |
|------------->| | | |
| | HID_get_input| | |
| | report | | |
| |------------->|------------------------| | |
| | | Read the DRAM data for| | |
| | | requested sensor and | | |
| | | create the HID input | | |
| | | report | | |
| | |------------------------| | |
| |Data received | | |
| | in HID report| | |
To |<-------------|<-------------| | |
Applications| | | | |
<-------| | | | |

45
Documentation/hid/hidraw.rst
View File

@@ -123,8 +123,49 @@ HIDIOCGFEATURE(len):
This ioctl will request a feature report from the device using the control
endpoint. The first byte of the supplied buffer should be set to the report
number of the requested report. For devices which do not use numbered
reports, set the first byte to 0. The report will be returned starting at
the first byte of the buffer (ie: the report number is not returned).
reports, set the first byte to 0. The returned report buffer will contain the
report number in the first byte, followed by the report data read from the
device. For devices which do not use numbered reports, the report data will
begin at the first byte of the returned buffer.
HIDIOCSINPUT(len):
Send an Input Report
This ioctl will send an input report to the device, using the control endpoint.
In most cases, setting an input HID report on a device is meaningless and has
no effect, but some devices may choose to use this to set or reset an initial
state of a report. The format of the buffer issued with this report is identical
to that of HIDIOCSFEATURE.
HIDIOCGINPUT(len):
Get an Input Report
This ioctl will request an input report from the device using the control
endpoint. This is slower on most devices where a dedicated In endpoint exists
for regular input reports, but allows the host to request the value of a
specific report number. Typically, this is used to request the initial states of
an input report of a device, before an application listens for normal reports via
the regular device read() interface. The format of the buffer issued with this report
is identical to that of HIDIOCGFEATURE.
HIDIOCSOUTPUT(len):
Send an Output Report
This ioctl will send an output report to the device, using the control endpoint.
This is slower on most devices where a dedicated Out endpoint exists for regular
output reports, but is added for completeness. Typically, this is used to set
the initial states of an output report of a device, before an application sends
updates via the regular device write() interface. The format of the buffer issued
with this report is identical to that of HIDIOCSFEATURE.
HIDIOCGOUTPUT(len):
Get an Output Report
This ioctl will request an output report from the device using the control
endpoint. Typically, this is used to retrive the initial state of
an output report of a device, before an application updates it as necessary either
via a HIDIOCSOUTPUT request, or the regular device write() interface. The format
of the buffer issued with this report is identical to that of HIDIOCGFEATURE.
Example
-------

1
Documentation/hid/index.rst
View File

@@ -16,3 +16,4 @@ Human Interface Devices (HID)
hid-alps
intel-ish-hid
amd-sfh-hid

26
MAINTAINERS
View File

@@ -956,6 +956,14 @@ S: Supported
F: arch/arm64/boot/dts/amd/amd-seattle-xgbe*.dtsi
F: drivers/net/ethernet/amd/xgbe/
AMD SENSOR FUSION HUB DRIVER
M: Nehal Shah <nehal-bakulchandra.shah@amd.com>
M: Sandeep Singh <sandeep.singh@amd.com>
L: linux-input@vger.kernel.org
S: Maintained
F: Documentation/hid/amd-sfh*
F: drivers/hid/amd-sfh-hid/
AMS AS73211 DRIVER
M: Christian Eggers <ceggers@arri.de>
L: linux-iio@vger.kernel.org
@@ -2018,7 +2026,7 @@ M: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
M: Gregory Clement <gregory.clement@bootlin.com>
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
S: Maintained
T: git git://git.infradead.org/linux-mvebu.git
T: git git://git.kernel.org/pub/scm/linux/kernel/git/gclement/mvebu.git
F: Documentation/devicetree/bindings/soc/dove/
F: arch/arm/boot/dts/dove*
F: arch/arm/boot/dts/orion5x*
@@ -2034,7 +2042,7 @@ M: Gregory Clement <gregory.clement@bootlin.com>
M: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
S: Maintained
T: git git://git.infradead.org/linux-mvebu.git
T: git git://git.kernel.org/pub/scm/linux/kernel/git/gclement/mvebu.git
F: arch/arm/boot/dts/armada*
F: arch/arm/boot/dts/kirkwood*
F: arch/arm/configs/mvebu_*_defconfig
@@ -2140,6 +2148,7 @@ W: http://linux-chenxing.org/
F: Documentation/devicetree/bindings/arm/mstar/*
F: arch/arm/boot/dts/mstar-*
F: arch/arm/mach-mstar/
F: include/dt-bindings/gpio/msc313-gpio.h
ARM/NEC MOBILEPRO 900/c MACHINE SUPPORT
M: Michael Petchkovsky <mkpetch@internode.on.net>
@@ -3386,7 +3395,7 @@ M: Florian Fainelli <f.fainelli@gmail.com>
L: netdev@vger.kernel.org
L: openwrt-devel@lists.openwrt.org (subscribers-only)
S: Supported
F: Documentation/devicetree/bindings/net/dsa/b53.txt
F: Documentation/devicetree/bindings/net/dsa/brcm,b53.yaml
F: drivers/net/dsa/b53/*
F: include/linux/platform_data/b53.h
@@ -11779,6 +11788,17 @@ M: Oliver Neukum <oliver@neukum.org>
S: Maintained
F: drivers/usb/image/microtek.*
MIKROTIK CRS3XX 98DX3236 BOARD SUPPORT
M: Luka Kovacic <luka.kovacic@sartura.hr>
M: Luka Perkov <luka.perkov@sartura.hr>
S: Maintained
F: arch/arm/boot/dts/armada-xp-crs305-1g-4s-bit.dts
F: arch/arm/boot/dts/armada-xp-crs305-1g-4s.dts
F: arch/arm/boot/dts/armada-xp-crs326-24g-2s-bit.dts
F: arch/arm/boot/dts/armada-xp-crs326-24g-2s.dts
F: arch/arm/boot/dts/armada-xp-crs328-4c-20s-4s-bit.dts
F: arch/arm/boot/dts/armada-xp-crs328-4c-20s-4s.dts
MIPI CCS, SMIA AND SMIA++ IMAGE SENSOR DRIVER
M: Sakari Ailus <sakari.ailus@linux.intel.com>
L: linux-media@vger.kernel.org

31
arch/arm/boot/dts/Makefile
View File

@@ -197,6 +197,7 @@ dtb-$(CONFIG_ARCH_EXYNOS4) += \
exynos4412-odroidx.dtb \
exynos4412-odroidx2.dtb \
exynos4412-origen.dtb \
exynos4412-p4note-n8010.dtb \
exynos4412-smdk4412.dtb \
exynos4412-tiny4412.dtb \
exynos4412-trats2.dtb
@@ -339,7 +340,10 @@ dtb-$(CONFIG_ARCH_LPC32XX) += \
lpc3250-ea3250.dtb \
lpc3250-phy3250.dtb
dtb-$(CONFIG_ARCH_NPCM7XX) += \
nuvoton-npcm750-evb.dtb
nuvoton-npcm730-gsj.dtb \
nuvoton-npcm730-kudo.dtb \
nuvoton-npcm750-evb.dtb \
nuvoton-npcm750-runbmc-olympus.dtb
dtb-$(CONFIG_MACH_MESON6) += \
meson6-atv1200.dtb
dtb-$(CONFIG_MACH_MESON8) += \
@@ -414,6 +418,7 @@ dtb-$(CONFIG_SOC_IMX53) += \
imx53-usbarmory.dtb \
imx53-voipac-bsb.dtb
dtb-$(CONFIG_SOC_IMX6Q) += \
imx6dl-alti6p.dtb \
imx6dl-apf6dev.dtb \
imx6dl-aristainetos_4.dtb \
imx6dl-aristainetos_7.dtb \
@@ -450,6 +455,7 @@ dtb-$(CONFIG_SOC_IMX6Q) += \
imx6dl-icore.dtb \
imx6dl-icore-mipi.dtb \
imx6dl-icore-rqs.dtb \
imx6dl-lanmcu.dtb \
imx6dl-mamoj.dtb \
imx6dl-nit6xlite.dtb \
imx6dl-nitrogen6x.dtb \
@@ -581,6 +587,7 @@ dtb-$(CONFIG_SOC_IMX6Q) += \
imx6qp-nitrogen6_max.dtb \
imx6qp-nitrogen6_som2.dtb \
imx6qp-phytec-mira-rdk-nand.dtb \
imx6qp-prtwd3.dtb \
imx6qp-sabreauto.dtb \
imx6qp-sabresd.dtb \
imx6qp-tx6qp-8037.dtb \
@@ -622,6 +629,7 @@ dtb-$(CONFIG_SOC_IMX6UL) += \
imx6ul-pico-dwarf.dtb \
imx6ul-pico-hobbit.dtb \
imx6ul-pico-pi.dtb \
imx6ul-phytec-segin-ff-rdk-emmc.dtb \
imx6ul-phytec-segin-ff-rdk-nand.dtb \
imx6ul-tx6ul-0010.dtb \
imx6ul-tx6ul-0011.dtb \
@@ -641,6 +649,8 @@ dtb-$(CONFIG_SOC_IMX7D) += \
imx7d-colibri-emmc-aster.dtb \
imx7d-colibri-emmc-eval-v3.dtb \
imx7d-colibri-eval-v3.dtb \
imx7d-flex-concentrator.dtb \
imx7d-flex-concentrator-mfg.dtb \
imx7d-mba7.dtb \
imx7d-meerkat96.dtb \
imx7d-nitrogen7.dtb \
@@ -1066,6 +1076,7 @@ dtb-$(CONFIG_ARCH_STM32) += \
stm32mp157a-iot-box.dtb \
stm32mp157a-stinger96.dtb \
stm32mp157c-dhcom-pdk2.dtb \
stm32mp157c-dhcom-picoitx.dtb \
stm32mp157c-dk2.dtb \
stm32mp157c-ed1.dtb \
stm32mp157c-ev1.dtb \
@@ -1192,6 +1203,7 @@ dtb-$(CONFIG_MACH_SUN8I) += \
sun8i-h3-nanopi-m1-plus.dtb \
sun8i-h3-nanopi-neo.dtb \
sun8i-h3-nanopi-neo-air.dtb \
sun8i-h3-nanopi-r1.dtb \
sun8i-h3-orangepi-2.dtb \
sun8i-h3-orangepi-lite.dtb \
sun8i-h3-orangepi-one.dtb \
@@ -1201,12 +1213,14 @@ dtb-$(CONFIG_MACH_SUN8I) += \
sun8i-h3-orangepi-plus2e.dtb \
sun8i-h3-orangepi-zero-plus2.dtb \
sun8i-h3-rervision-dvk.dtb \
sun8i-h3-zeropi.dtb \
sun8i-h3-emlid-neutis-n5h3-devboard.dtb \
sun8i-r16-bananapi-m2m.dtb \
sun8i-r16-nintendo-nes-classic.dtb \
sun8i-r16-nintendo-super-nes-classic.dtb \
sun8i-r16-parrot.dtb \
sun8i-r40-bananapi-m2-ultra.dtb \
sun8i-s3-elimo-initium.dtb \
sun8i-s3-lichee-zero-plus.dtb \
sun8i-s3-pinecube.dtb \
sun8i-t3-cqa3t-bv3.dtb \
@@ -1241,7 +1255,8 @@ dtb-$(CONFIG_ARCH_TEGRA_3x_SOC) += \
tegra30-beaver.dtb \
tegra30-cardhu-a02.dtb \
tegra30-cardhu-a04.dtb \
tegra30-colibri-eval-v3.dtb
tegra30-colibri-eval-v3.dtb \
tegra30-ouya.dtb
dtb-$(CONFIG_ARCH_TEGRA_114_SOC) += \
tegra114-dalmore.dtb \
tegra114-roth.dtb \
@@ -1302,6 +1317,7 @@ dtb-$(CONFIG_ARCH_ZYNQ) += \
zynq-zc770-xm013.dtb \
zynq-zed.dtb \
zynq-zturn.dtb \
zynq-zturn-v5.dtb \
zynq-zybo.dtb \
zynq-zybo-z7.dtb
dtb-$(CONFIG_MACH_ARMADA_370) += \
@@ -1319,6 +1335,7 @@ dtb-$(CONFIG_MACH_ARMADA_370) += \
dtb-$(CONFIG_MACH_ARMADA_375) += \
armada-375-db.dtb
dtb-$(CONFIG_MACH_ARMADA_38X) += \
armada-382-rd-ac3x-48g4x2xl.dtb \
armada-385-clearfog-gtr-s4.dtb \
armada-385-clearfog-gtr-l8.dtb \
armada-385-db-88f6820-amc.dtb \
@@ -1340,6 +1357,12 @@ dtb-$(CONFIG_MACH_ARMADA_39X) += \
armada-398-db.dtb
dtb-$(CONFIG_MACH_ARMADA_XP) += \
armada-xp-axpwifiap.dtb \
armada-xp-crs305-1g-4s.dtb \
armada-xp-crs305-1g-4s-bit.dtb \
armada-xp-crs326-24g-2s.dtb \
armada-xp-crs326-24g-2s-bit.dtb \
armada-xp-crs328-4c-20s-4s.dtb \
armada-xp-crs328-4c-20s-4s-bit.dtb \
armada-xp-db.dtb \
armada-xp-db-dxbc2.dtb \
armada-xp-db-xc3-24g4xg.dtb \
@@ -1372,6 +1395,7 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += \
dtb-$(CONFIG_ARCH_MILBEAUT) += milbeaut-m10v-evb.dtb
dtb-$(CONFIG_ARCH_MSTARV7) += \
mstar-infinity-msc313-breadbee_crust.dtb \
mstar-infinity2m-ssd202d-ssd201htv2.dtb \
mstar-infinity3-msc313e-breadbee.dtb \
mstar-mercury5-ssc8336n-midrived08.dtb
dtb-$(CONFIG_ARCH_ZX) += zx296702-ad1.dtb
@@ -1381,7 +1405,9 @@ dtb-$(CONFIG_ARCH_ASPEED) += \
aspeed-bmc-amd-ethanolx.dtb \
aspeed-bmc-arm-centriq2400-rep.dtb \
aspeed-bmc-arm-stardragon4800-rep2.dtb \
aspeed-bmc-bytedance-g220a.dtb \
aspeed-bmc-facebook-cmm.dtb \
aspeed-bmc-facebook-galaxy100.dtb \
aspeed-bmc-facebook-minipack.dtb \
aspeed-bmc-facebook-tiogapass.dtb \
aspeed-bmc-facebook-wedge40.dtb \
@@ -1390,6 +1416,7 @@ dtb-$(CONFIG_ARCH_ASPEED) += \
aspeed-bmc-facebook-yamp.dtb \
aspeed-bmc-facebook-yosemitev2.dtb \
aspeed-bmc-ibm-rainier.dtb \
aspeed-bmc-ibm-rainier-4u.dtb \
aspeed-bmc-intel-s2600wf.dtb \
aspeed-bmc-inspur-fp5280g2.dtb \
aspeed-bmc-lenovo-hr630.dtb \

2
arch/arm/boot/dts/am335x-baltos.dtsi
View File

@@ -168,7 +168,7 @@
AM33XX_PADCONF(AM335X_PIN_GPMC_AD6, PIN_INPUT_PULLUP, MUX_MODE0) /* gpmc_ad6.gpmc_ad6 */
AM33XX_PADCONF(AM335X_PIN_GPMC_AD7, PIN_INPUT_PULLUP, MUX_MODE0) /* gpmc_ad7.gpmc_ad7 */
AM33XX_PADCONF(AM335X_PIN_GPMC_WAIT0, PIN_INPUT_PULLUP, MUX_MODE0) /* gpmc_wait0.gpmc_wait0 */
AM33XX_PADCONF(AM335X_PIN_GPMC_WPN, PIN_INPUT_PULLUP, MUX_MODE7) /* gpmc_wpn.gpio0_30 */
AM33XX_PADCONF(AM335X_PIN_GPMC_WPN, PIN_INPUT_PULLUP, MUX_MODE7) /* gpmc_wpn.gpio0_31 */
AM33XX_PADCONF(AM335X_PIN_GPMC_CSN0, PIN_OUTPUT, MUX_MODE0) /* gpmc_csn0.gpmc_csn0 */
AM33XX_PADCONF(AM335X_PIN_GPMC_ADVN_ALE, PIN_OUTPUT, MUX_MODE0) /* gpmc_advn_ale.gpmc_advn_ale */
AM33XX_PADCONF(AM335X_PIN_GPMC_OEN_REN, PIN_OUTPUT, MUX_MODE0) /* gpmc_oen_ren.gpmc_oen_ren */

54
arch/arm/boot/dts/am335x-boneblue.dts
View File

@@ -241,6 +241,30 @@
AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_OUTPUT, MUX_MODE7) /* (M16) gmii1_rxd0.gpio2[21] */
>;
};
/* E1 */
eqep0_pins: pinmux_eqep0_pins {
pinctrl-single,pins = <
AM33XX_PADCONF(AM335X_PIN_MCASP0_AXR0, PIN_INPUT, MUX_MODE1) /* (B12) mcasp0_aclkr.eQEP0A_in */
AM33XX_PADCONF(AM335X_PIN_MCASP0_FSR, PIN_INPUT, MUX_MODE1) /* (C13) mcasp0_fsr.eQEP0B_in */
>;
};
/* E2 */
eqep1_pins: pinmux_eqep1_pins {
pinctrl-single,pins = <
AM33XX_PADCONF(AM335X_PIN_LCD_DATA12, PIN_INPUT, MUX_MODE2) /* (V2) lcd_data12.eQEP1A_in */
AM33XX_PADCONF(AM335X_PIN_LCD_DATA13, PIN_INPUT, MUX_MODE2) /* (V3) lcd_data13.eQEP1B_in */
>;
};
/* E3 */
eqep2_pins: pinmux_eqep2_pins {
pinctrl-single,pins = <
AM33XX_PADCONF(AM335X_PIN_GPMC_AD12, PIN_INPUT, MUX_MODE4) /* (T12) gpmc_ad12.eQEP2A_in */
AM33XX_PADCONF(AM335X_PIN_GPMC_AD13, PIN_INPUT, MUX_MODE4) /* (R12) gpmc_ad13.eQEP2B_in */
>;
};
};
&uart0 {
@@ -419,3 +443,33 @@
line-name = "LS_BUF_EN";
};
};
&epwmss0 {
status = "okay";
};
&eqep0 {
pinctrl-names = "default";
pinctrl-0 = <&eqep0_pins>;
status = "okay";
};
&epwmss1 {
status = "okay";
};
&eqep1 {
pinctrl-names = "default";
pinctrl-0 = <&eqep1_pins>;
status = "okay";
};
&epwmss2 {
status = "okay";
};
&eqep2 {
pinctrl-names = "default";
pinctrl-0 = <&eqep2_pins>;
status = "okay";
};

2
arch/arm/boot/dts/am335x-cm-t335.dts
View File

@@ -122,7 +122,7 @@
AM33XX_PADCONF(AM335X_PIN_GPMC_AD6, PIN_INPUT_PULLUP, MUX_MODE0)
AM33XX_PADCONF(AM335X_PIN_GPMC_AD7, PIN_INPUT_PULLUP, MUX_MODE0)
AM33XX_PADCONF(AM335X_PIN_GPMC_WAIT0, PIN_INPUT_PULLUP, MUX_MODE0)
/* gpmc_wpn.gpio0_30 */
/* gpmc_wpn.gpio0_31 */
AM33XX_PADCONF(AM335X_PIN_GPMC_WPN, PIN_INPUT_PULLUP, MUX_MODE7)
AM33XX_PADCONF(AM335X_PIN_GPMC_CSN0, PIN_OUTPUT, MUX_MODE0)
AM33XX_PADCONF(AM335X_PIN_GPMC_ADVN_ALE, PIN_OUTPUT, MUX_MODE0)

2
arch/arm/boot/dts/am335x-evm.dts
View File

@@ -229,7 +229,7 @@
AM33XX_PADCONF(AM335X_PIN_GPMC_AD6, PIN_INPUT_PULLUP, MUX_MODE0)
AM33XX_PADCONF(AM335X_PIN_GPMC_AD7, PIN_INPUT_PULLUP, MUX_MODE0)
AM33XX_PADCONF(AM335X_PIN_GPMC_WAIT0, PIN_INPUT_PULLUP, MUX_MODE0)
AM33XX_PADCONF(AM335X_PIN_GPMC_WPN, PIN_INPUT_PULLUP, MUX_MODE7) /* gpmc_wpn.gpio0_30 */
AM33XX_PADCONF(AM335X_PIN_GPMC_WPN, PIN_INPUT_PULLUP, MUX_MODE7) /* gpmc_wpn.gpio0_31 */
AM33XX_PADCONF(AM335X_PIN_GPMC_CSN0, PIN_OUTPUT, MUX_MODE0)
AM33XX_PADCONF(AM335X_PIN_GPMC_ADVN_ALE, PIN_OUTPUT, MUX_MODE0)
AM33XX_PADCONF(AM335X_PIN_GPMC_OEN_REN, PIN_OUTPUT, MUX_MODE0)

2
arch/arm/boot/dts/am335x-igep0033.dtsi
View File

@@ -70,7 +70,7 @@
AM33XX_PADCONF(AM335X_PIN_GPMC_AD6, PIN_INPUT_PULLUP, MUX_MODE0)
AM33XX_PADCONF(AM335X_PIN_GPMC_AD7, PIN_INPUT_PULLUP, MUX_MODE0)
AM33XX_PADCONF(AM335X_PIN_GPMC_WAIT0, PIN_INPUT_PULLUP, MUX_MODE0)
AM33XX_PADCONF(AM335X_PIN_GPMC_WPN, PIN_INPUT_PULLUP, MUX_MODE7) /* gpmc_wpn.gpio0_30 */
AM33XX_PADCONF(AM335X_PIN_GPMC_WPN, PIN_INPUT_PULLUP, MUX_MODE7) /* gpmc_wpn.gpio0_31 */
AM33XX_PADCONF(AM335X_PIN_GPMC_CSN0, PIN_OUTPUT, MUX_MODE0)
AM33XX_PADCONF(AM335X_PIN_GPMC_ADVN_ALE, PIN_OUTPUT, MUX_MODE0)
AM33XX_PADCONF(AM335X_PIN_GPMC_OEN_REN, PIN_OUTPUT, MUX_MODE0)

27
arch/arm/boot/dts/am33xx-l4.dtsi
View File

@@ -1923,6 +1923,15 @@
status = "disabled";
};
eqep0: counter@180 {
compatible = "ti,am3352-eqep";
reg = <0x180 0x80>;
clocks = <&l4ls_gclk>;
clock-names = "sysclkout";
interrupts = <79>;
status = "disabled";
};
ehrpwm0: pwm@200 {
compatible = "ti,am3352-ehrpwm",
"ti,am33xx-ehrpwm";
@@ -1975,6 +1984,15 @@
status = "disabled";
};
eqep1: counter@180 {
compatible = "ti,am3352-eqep";
reg = <0x180 0x80>;
clocks = <&l4ls_gclk>;
clock-names = "sysclkout";
interrupts = <88>;
status = "disabled";
};
ehrpwm1: pwm@200 {
compatible = "ti,am3352-ehrpwm",
"ti,am33xx-ehrpwm";
@@ -2027,6 +2045,15 @@
status = "disabled";
};
eqep2: counter@180 {
compatible = "ti,am3352-eqep";
reg = <0x180 0x80>;
clocks = <&l4ls_gclk>;
clock-names = "sysclkout";
interrupts = <89>;
status = "disabled";
};
ehrpwm2: pwm@200 {
compatible = "ti,am3352-ehrpwm",
"ti,am33xx-ehrpwm";

4
arch/arm/boot/dts/am437x-l4.dtsi
View File

@@ -2388,7 +2388,7 @@
ranges = <0 0 0x20000>;
usb1: usb@10000 {
compatible = "synopsys,dwc3";
compatible = "snps,dwc3";
reg = <0x10000 0x10000>;
interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
@@ -2468,7 +2468,7 @@
ranges = <0 0 0x20000>;
usb2: usb@10000 {
compatible = "synopsys,dwc3";
compatible = "snps,dwc3";
reg = <0x10000 0x10000>;
interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>,

2
arch/arm/boot/dts/armada-375.dtsi
View File

@@ -426,7 +426,7 @@
status = "disabled";
};
usb2: usb3@58000 {
usb2: usb@58000 {
compatible = "marvell,armada-375-xhci";
reg = <0x58000 0x20000>,<0x5b880 0x80>;
interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;

112
arch/arm/boot/dts/armada-382-rd-ac3x-48g4x2xl.dts Normal file
View File

@@ -0,0 +1,112 @@
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
* Device Tree file for Marvell Armada 382 reference board
* (RD-AC3X-48G4X2XL)
*
* Copyright (C) 2020 Allied Telesis Labs
*/
/dts-v1/;
#include "armada-385.dtsi"
#include <dt-bindings/gpio/gpio.h>
/ {
model = "Marvell Armada 382 RD-AC3X";
compatible = "marvell,rd-ac3x-48g4x2xl", "marvell,rd-ac3x",
"marvell,armada385", "marvell,armada380";
chosen {
stdout-path = "serial0:115200n8";
};
aliases {
ethernet0 = &eth1;
};
memory {
device_type = "memory";
reg = <0x00000000 0x20000000>; /* 512MB */
};
soc {
ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000>;
};
};
&i2c0 {
pinctrl-names = "default";
pinctrl-0 = <&i2c0_pins>;
status = "okay";
eeprom@53{
compatible = "atmel,24c64";
reg = <0x53>;
};
/* CPLD device present at 0x3c. Function unknown */
};
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_pins>;
status = "okay";
};
&eth1 {
status = "okay";
phy = <&phy0>;
phy-mode = "rgmii-id";
};
&mdio {
pinctrl-names = "default";
pinctrl-0 = <&mdio_pins>;
phy0: ethernet-phy@0 {
reg = <0>;
};
};
&pciec {
status = "okay";
};
&pcie1 {
/* Port 0, Lane 0 */
status = "okay";
};
&nand_controller {
status = "okay";
nand@0 {
reg = <0>;
label = "pxa3xx_nand-0";
nand-rb = <0>;
nand-on-flash-bbt;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
reg = <0x00000000 0x00500000>;
label = "u-boot";
};
partition@500000{
reg = <0x00500000 0x00400000>;
label = "u-boot env";
};
partition@900000{
reg = <0x00900000 0x3F700000>;
label = "user";
};
};
};
};
&refclk {
clock-frequency = <200000000>;
};

179
arch/arm/boot/dts/armada-385-turris-omnia.dts
View File

@@ -12,6 +12,7 @@
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/leds/common.h>
#include "armada-385.dtsi"
/ {
@@ -82,6 +83,32 @@
};
};
};
sfp: sfp {
compatible = "sff,sfp";
i2c-bus = <&sfp_i2c>;
tx-fault-gpios = <&pcawan 0 GPIO_ACTIVE_HIGH>;
tx-disable-gpios = <&pcawan 1 GPIO_ACTIVE_HIGH>;
rate-select0-gpios = <&pcawan 2 GPIO_ACTIVE_HIGH>;
los-gpios = <&pcawan 3 GPIO_ACTIVE_HIGH>;
mod-def0-gpios = <&pcawan 4 GPIO_ACTIVE_LOW>;
maximum-power-milliwatt = <3000>;
/*
* For now this has to be enabled at boot time by U-Boot when
* a SFP module is present. Read more in the comment in the
* eth2 node below.
*/
status = "disabled";
};
};
&bm {
status = "okay";
};
&bm_bppi {
status = "okay";
};
/* Connected to 88E6176 switch, port 6 */
@@ -90,6 +117,9 @@
pinctrl-0 = <&ge0_rgmii_pins>;
status = "okay";
phy-mode = "rgmii";
buffer-manager = <&bm>;
bm,pool-long = <0>;
bm,pool-short = <3>;
fixed-link {
speed = <1000>;
@@ -103,6 +133,9 @@
pinctrl-0 = <&ge1_rgmii_pins>;
status = "okay";
phy-mode = "rgmii";
buffer-manager = <&bm>;
bm,pool-long = <1>;
bm,pool-short = <3>;
fixed-link {
speed = <1000>;
@@ -112,9 +145,23 @@
/* WAN port */
&eth2 {
/*
* eth2 is connected via a multiplexor to both the SFP cage and to
* ethernet-phy@1. The multiplexor switches the signal to SFP cage when
* a SFP module is present, as determined by the mode-def0 GPIO.
*
* Until kernel supports this configuration properly, in case SFP module
* is present, U-Boot has to enable the sfp node above, remove phy
* handle and add managed = "in-band-status" property.
*/
status = "okay";
phy-mode = "sgmii";
phy = <&phy1>;
phy-handle = <&phy1>;
phys = <&comphy5 2>;
sfp = <&sfp>;
buffer-manager = <&bm>;
bm,pool-long = <2>;
bm,pool-short = <3>;
};
&i2c0 {
@@ -127,7 +174,6 @@
#address-cells = <1>;
#size-cells = <0>;
reg = <0x70>;
status = "okay";
i2c@0 {
#address-cells = <1>;
@@ -135,7 +181,115 @@
reg = <0>;
/* STM32F0 command interface at address 0x2a */
/* leds device (in STM32F0) at address 0x2b */
led-controller@2b {
compatible = "cznic,turris-omnia-leds";
reg = <0x2b>;
#address-cells = <1>;
#size-cells = <0>;
/*
* LEDs are controlled by MCU (STM32F0) at
* address 0x2b.
*
* The driver does not support HW control mode
* for the LEDs yet. Disable the LEDs for now.
*
* Also LED functions are not stable yet:
* - there are 3 LEDs connected via MCU to PCIe
* ports. One of these ports supports mSATA.
* There is no mSATA nor PCIe function.
* For now we use LED_FUNCTION_WLAN, since
* in most cases users have wifi cards in
* these slots
* - there are 2 LEDs dedicated for user: A and
* B. Again there is no such function defined.
* For now we use LED_FUNCTION_INDICATOR
*/
status = "disabled";
multi-led@0 {
reg = <0x0>;
color = <LED_COLOR_ID_RGB>;
function = LED_FUNCTION_INDICATOR;
function-enumerator = <2>;
};
multi-led@1 {
reg = <0x1>;
color = <LED_COLOR_ID_RGB>;
function = LED_FUNCTION_INDICATOR;
function-enumerator = <1>;
};
multi-led@2 {
reg = <0x2>;
color = <LED_COLOR_ID_RGB>;
function = LED_FUNCTION_WLAN;
function-enumerator = <3>;
};
multi-led@3 {
reg = <0x3>;
color = <LED_COLOR_ID_RGB>;
function = LED_FUNCTION_WLAN;
function-enumerator = <2>;
};
multi-led@4 {
reg = <0x4>;
color = <LED_COLOR_ID_RGB>;
function = LED_FUNCTION_WLAN;
function-enumerator = <1>;
};
multi-led@5 {
reg = <0x5>;
color = <LED_COLOR_ID_RGB>;
function = LED_FUNCTION_WAN;
};
multi-led@6 {
reg = <0x6>;
color = <LED_COLOR_ID_RGB>;
function = LED_FUNCTION_LAN;
function-enumerator = <4>;
};
multi-led@7 {
reg = <0x7>;
color = <LED_COLOR_ID_RGB>;
function = LED_FUNCTION_LAN;
function-enumerator = <3>;
};
multi-led@8 {
reg = <0x8>;
color = <LED_COLOR_ID_RGB>;
function = LED_FUNCTION_LAN;
function-enumerator = <2>;
};
multi-led@9 {
reg = <0x9>;
color = <LED_COLOR_ID_RGB>;
function = LED_FUNCTION_LAN;
function-enumerator = <1>;
};
multi-led@a {
reg = <0xa>;
color = <LED_COLOR_ID_RGB>;
function = LED_FUNCTION_LAN;
function-enumerator = <0>;
};
multi-led@b {
reg = <0xb>;
color = <LED_COLOR_ID_RGB>;
function = LED_FUNCTION_POWER;
};
};
eeprom@54 {
compatible = "atmel,24c64";
@@ -177,7 +331,7 @@
/* routed to PCIe2 connector (CN62A) */
};
i2c@4 {
sfp_i2c: i2c@4 {
#address-cells = <1>;
#size-cells = <0>;
reg = <4>;
@@ -232,9 +386,8 @@
pinctrl-0 = <&mdio_pins>;
status = "okay";
phy1: phy@1 {
status = "okay";
compatible = "ethernet-phy-id0141.0DD1", "ethernet-phy-ieee802.3-c22";
phy1: ethernet-phy@1 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <1>;
/* irq is connected to &pcawan pin 7 */
@@ -242,13 +395,18 @@
/* Switch MV88E6176 at address 0x10 */
switch@10 {
pinctrl-names = "default";
pinctrl-0 = <&swint_pins>;
compatible = "marvell,mv88e6085";
#address-cells = <1>;
#size-cells = <0>;
dsa,member = <0 0>;
dsa,member = <0 0>;
reg = <0x10>;
interrupt-parent = <&gpio1>;
interrupts = <13 IRQ_TYPE_LEVEL_LOW>;
ports {
#address-cells = <1>;
#size-cells = <0>;
@@ -301,6 +459,11 @@
marvell,function = "gpio";
};
swint_pins: swint-pins {
marvell,pins = "mpp45";
marvell,function = "gpio";
};
spi0cs0_pins: spi0cs0-pins {
marvell,pins = "mpp25";
marvell,function = "spi0";

4
arch/arm/boot/dts/armada-388-clearfog.dts
View File

@@ -73,13 +73,13 @@
* 14-SFP_TX_DISABLE
* 15-SFP_MOD_DEF0
*/
pcie2_0_clkreq {
pcie2-0-clkreq-hog {
gpio-hog;
gpios = <4 GPIO_ACTIVE_LOW>;
input;
line-name = "pcie2.0-clkreq";
};
pcie2_0_w_disable {
pcie2-0-w-disable-hog {
gpio-hog;
gpios = <7 GPIO_ACTIVE_LOW>;
output-low;

10
arch/arm/boot/dts/armada-388-clearfog.dtsi
View File

@@ -141,31 +141,31 @@
#gpio-cells = <2>;
reg = <0x20>;
pcie1_0_clkreq {
pcie1-0-clkreq-hog {
gpio-hog;
gpios = <0 GPIO_ACTIVE_LOW>;
input;
line-name = "pcie1.0-clkreq";
};
pcie1_0_w_disable {
pcie1-0-w-disable-hog {
gpio-hog;
gpios = <3 GPIO_ACTIVE_LOW>;
output-low;
line-name = "pcie1.0-w-disable";
};
usb3_ilimit {
usb3-ilimit-hog {
gpio-hog;
gpios = <5 GPIO_ACTIVE_LOW>;
input;
line-name = "usb3-current-limit";
};
usb3_power {
usb3-power-hog {
gpio-hog;
gpios = <6 GPIO_ACTIVE_HIGH>;
output-high;
line-name = "usb3-power";
};
m2_devslp {
m2-devslp-hog {
gpio-hog;
gpios = <11 GPIO_ACTIVE_HIGH>;
output-low;

6
arch/arm/boot/dts/armada-388-helios4.dts
View File

@@ -166,19 +166,19 @@
interrupt-controller;
#interrupt-cells = <2>;
board_rev_bit_0 {
board-rev-bit-0-hog {
gpio-hog;
gpios = <0 GPIO_ACTIVE_LOW>;
input;
line-name = "board-rev-0";
};
board_rev_bit_1 {
board-rev-bit-1-hog {
gpio-hog;
gpios = <1 GPIO_ACTIVE_LOW>;
input;
line-name = "board-rev-1";
};
usb3_ilimit {
usb3-ilimit-hog {
gpio-hog;
gpios = <5 GPIO_ACTIVE_HIGH>;
input;

12
arch/arm/boot/dts/armada-xp-98dx3236.dtsi
View File

@@ -264,11 +264,8 @@
&i2c0 {
compatible = "marvell,mv78230-i2c", "marvell,mv64xxx-i2c";
reg = <0x11000 0x100>;
};
&i2c1 {
compatible = "marvell,mv78230-i2c", "marvell,mv64xxx-i2c";
reg = <0x11100 0x100>;
pinctrl-names = "default";
pinctrl-0 = <&i2c0_pins>;
};
&mpic {
@@ -324,6 +321,11 @@
"mpp2", "mpp3";
marvell,function = "spi0";
};
i2c0_pins: i2c-pins-0 {
marvell,pins = "mpp14", "mpp15";
marvell,function = "i2c0";
};
};
&spi0 {

43
arch/arm/boot/dts/armada-xp-crs305-1g-4s-bit.dts Normal file
View File

@@ -0,0 +1,43 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Device Tree file for MikroTik CRS305-1G-4S+ Bit board
*
* Copyright (C) 2020 Sartura Ltd.
* Author: Luka Kovacic <luka.kovacic@sartura.hr>
*/
#include "armada-xp-crs305-1g-4s.dtsi"
/ {
model = "MikroTik CRS305-1G-4S+ Bit";
};
&spi0 {
status = "okay";
spi-flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "jedec,spi-nor";
reg = <0>; /* Chip select 0 */
spi-max-frequency = <108000000>;
m25p,fast-read;
partition@u-boot {
reg = <0x00000000 0x001f0000>;
label = "u-boot";
};
partition@u-boot-env {
reg = <0x001f0000 0x00010000>;
label = "u-boot-env";
};
partition@ubi1 {
reg = <0x00200000 0x03f00000>;
label = "ubi1";
};
partition@ubi2 {
reg = <0x04100000 0x03f00000>;
label = "ubi2";
};
};
};

17
arch/arm/boot/dts/armada-xp-crs305-1g-4s.dts Normal file
View File

@@ -0,0 +1,17 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Device Tree file for MikroTik CRS305-1G-4S+ board
*
* Copyright (C) 2020 Sartura Ltd.
* Author: Luka Kovacic <luka.kovacic@sartura.hr>
*/
#include "armada-xp-crs305-1g-4s.dtsi"
/ {
model = "MikroTik CRS305-1G-4S+";
};
&spi0 {
status = "okay";
};

104
arch/arm/boot/dts/armada-xp-crs305-1g-4s.dtsi Normal file
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@@ -0,0 +1,104 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Device Tree file for CRS305-1G-4S board
*
* Copyright (C) 2016 Allied Telesis Labs
* Copyright (C) 2020 Sartura Ltd.
*
* Based on armada-xp-db.dts
*
* Note: this Device Tree assumes that the bootloader has remapped the
* internal registers to 0xf1000000 (instead of the default
* 0xd0000000). The 0xf1000000 is the default used by the recent,
* DT-capable, U-Boot bootloaders provided by Marvell. Some earlier
* boards were delivered with an older version of the bootloader that
* left internal registers mapped at 0xd0000000. If you are in this
* situation, you should either update your bootloader (preferred
* solution) or the below Device Tree should be adjusted.
*/
/dts-v1/;
#include "armada-xp-98dx3236.dtsi"
/ {
model = "CRS305-1G-4S+";
compatible = "mikrotik,crs305-1g-4s", "marvell,armadaxp-98dx3236", "marvell,armada-370-xp";
chosen {
bootargs = "console=ttyS0,115200 earlyprintk";
};
memory {
device_type = "memory";
reg = <0 0x00000000 0 0x20000000>; /* 512 MB */
};
};
&L2 {
arm,parity-enable;
marvell,ecc-enable;
};
&devbus_bootcs {
status = "okay";
/* Device Bus parameters are required */
/* Read parameters */
devbus,bus-width = <16>;
devbus,turn-off-ps = <60000>;
devbus,badr-skew-ps = <0>;
devbus,acc-first-ps = <124000>;
devbus,acc-next-ps = <248000>;
devbus,rd-setup-ps = <0>;
devbus,rd-hold-ps = <0>;
/* Write parameters */
devbus,sync-enable = <0>;
devbus,wr-high-ps = <60000>;
devbus,wr-low-ps = <60000>;
devbus,ale-wr-ps = <60000>;
};
&uart0 {
status = "okay";
};
&uart1 {
status = "okay";
};
&i2c0 {
clock-frequency = <100000>;
status = "okay";
};
&usb0 {
status = "okay";
};
&spi0 {
status = "okay";
spi-flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "jedec,spi-nor";
reg = <0>; /* Chip select 0 */
spi-max-frequency = <108000000>;
m25p,fast-read;
partition@u-boot {
reg = <0x00000000 0x001f0000>;
label = "u-boot";
};
partition@u-boot-env {
reg = <0x001f0000 0x00010000>;
label = "u-boot-env";
};
partition@ubi1 {
reg = <0x00200000 0x00e00000>;
label = "ubi1";
};
};
};

43
arch/arm/boot/dts/armada-xp-crs326-24g-2s-bit.dts Normal file
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@@ -0,0 +1,43 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Device Tree file for MikroTik CRS326-24G-2S+ Bit board
*
* Copyright (C) 2020 Sartura Ltd.
* Author: Luka Kovacic <luka.kovacic@sartura.hr>
*/
#include "armada-xp-crs326-24g-2s.dtsi"
/ {
model = "MikroTik CRS326-24G-2S+ Bit";
};
&spi0 {
status = "okay";
spi-flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "jedec,spi-nor";
reg = <0>; /* Chip select 0 */
spi-max-frequency = <108000000>;
m25p,fast-read;
partition@u-boot {
reg = <0x00000000 0x001f0000>;
label = "u-boot";
};
partition@u-boot-env {
reg = <0x001f0000 0x00010000>;
label = "u-boot-env";
};
partition@ubi1 {
reg = <0x00200000 0x03f00000>;
label = "ubi1";
};
partition@ubi2 {
reg = <0x04100000 0x03f00000>;
label = "ubi2";
};
};
};

17
arch/arm/boot/dts/armada-xp-crs326-24g-2s.dts Normal file
View File

@@ -0,0 +1,17 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Device Tree file for MikroTik CRS326-24G-2S+ board
*
* Copyright (C) 2020 Sartura Ltd.
* Author: Luka Kovacic <luka.kovacic@sartura.hr>
*/
#include "armada-xp-crs326-24g-2s.dtsi"
/ {
model = "MikroTik CRS326-24G-2S+";
};
&spi0 {
status = "okay";
};

104
arch/arm/boot/dts/armada-xp-crs326-24g-2s.dtsi Normal file
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@@ -0,0 +1,104 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Device Tree file for CRS326-24G-2S board
*
* Copyright (C) 2016 Allied Telesis Labs
* Copyright (C) 2020 Sartura Ltd.
*
* Based on armada-xp-db.dts
*
* Note: this Device Tree assumes that the bootloader has remapped the
* internal registers to 0xf1000000 (instead of the default
* 0xd0000000). The 0xf1000000 is the default used by the recent,
* DT-capable, U-Boot bootloaders provided by Marvell. Some earlier
* boards were delivered with an older version of the bootloader that
* left internal registers mapped at 0xd0000000. If you are in this
* situation, you should either update your bootloader (preferred
* solution) or the below Device Tree should be adjusted.
*/
/dts-v1/;
#include "armada-xp-98dx3236.dtsi"
/ {
model = "CRS326-24G-2S+";
compatible = "mikrotik,crs326-24g-2s", "marvell,armadaxp-98dx3236", "marvell,armada-370-xp";
chosen {
bootargs = "console=ttyS0,115200 earlyprintk";
};
memory {
device_type = "memory";
reg = <0 0x00000000 0 0x20000000>; /* 512 MB */
};
};
&L2 {
arm,parity-enable;
marvell,ecc-enable;
};
&devbus_bootcs {
status = "okay";
/* Device Bus parameters are required */
/* Read parameters */
devbus,bus-width = <16>;
devbus,turn-off-ps = <60000>;
devbus,badr-skew-ps = <0>;
devbus,acc-first-ps = <124000>;
devbus,acc-next-ps = <248000>;
devbus,rd-setup-ps = <0>;
devbus,rd-hold-ps = <0>;
/* Write parameters */
devbus,sync-enable = <0>;
devbus,wr-high-ps = <60000>;
devbus,wr-low-ps = <60000>;
devbus,ale-wr-ps = <60000>;
};
&uart0 {
status = "okay";
};
&uart1 {
status = "okay";
};
&i2c0 {
clock-frequency = <100000>;
status = "okay";
};
&usb0 {
status = "okay";
};
&spi0 {
status = "okay";
spi-flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "jedec,spi-nor";
reg = <0>; /* Chip select 0 */
spi-max-frequency = <108000000>;
m25p,fast-read;
partition@u-boot {
reg = <0x00000000 0x001f0000>;
label = "u-boot";
};
partition@u-boot-env {
reg = <0x001f0000 0x00010000>;
label = "u-boot-env";
};
partition@ubi1 {
reg = <0x00200000 0x00e00000>;
label = "ubi1";
};
};
};

43
arch/arm/boot/dts/armada-xp-crs328-4c-20s-4s-bit.dts Normal file
View File

@@ -0,0 +1,43 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Device Tree file for MikroTik CRS328-4C-20S-4S+ Bit board
*
* Copyright (C) 2020 Sartura Ltd.
* Author: Luka Kovacic <luka.kovacic@sartura.hr>
*/
#include "armada-xp-crs328-4c-20s-4s.dtsi"
/ {
model = "MikroTik CRS328-4C-20S-4S+ Bit";
};
&spi0 {
status = "okay";
spi-flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "jedec,spi-nor";
reg = <0>; /* Chip select 0 */
spi-max-frequency = <108000000>;
m25p,fast-read;
partition@u-boot {
reg = <0x00000000 0x001f0000>;
label = "u-boot";
};
partition@u-boot-env {
reg = <0x001f0000 0x00010000>;
label = "u-boot-env";
};
partition@ubi1 {
reg = <0x00200000 0x03f00000>;
label = "ubi1";
};
partition@ubi2 {
reg = <0x04100000 0x03f00000>;
label = "ubi2";
};
};
};

17
arch/arm/boot/dts/armada-xp-crs328-4c-20s-4s.dts Normal file
View File

@@ -0,0 +1,17 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Device Tree file for MikroTik CRS328-4C-20S-4S+ board
*
* Copyright (C) 2020 Sartura Ltd.
* Author: Luka Kovacic <luka.kovacic@sartura.hr>
*/
#include "armada-xp-crs328-4c-20s-4s.dtsi"
/ {
model = "MikroTik CRS328-4C-20S-4S+";
};
&spi0 {
status = "okay";
};

104
arch/arm/boot/dts/armada-xp-crs328-4c-20s-4s.dtsi Normal file
View File

@@ -0,0 +1,104 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Device Tree file for CRS328-4C-20S-4S+ board
*
* Copyright (C) 2016 Allied Telesis Labs
* Copyright (C) 2020 Sartura Ltd.
*
* Based on armada-xp-db.dts
*
* Note: this Device Tree assumes that the bootloader has remapped the
* internal registers to 0xf1000000 (instead of the default
* 0xd0000000). The 0xf1000000 is the default used by the recent,
* DT-capable, U-Boot bootloaders provided by Marvell. Some earlier
* boards were delivered with an older version of the bootloader that
* left internal registers mapped at 0xd0000000. If you are in this
* situation, you should either update your bootloader (preferred
* solution) or the below Device Tree should be adjusted.
*/
/dts-v1/;
#include "armada-xp-98dx3236.dtsi"
/ {
model = "CRS328-4C-20S-4S+";
compatible = "mikrotik,crs328-4c-20s-4s", "marvell,armadaxp-98dx3236", "marvell,armada-370-xp";
chosen {
bootargs = "console=ttyS0,115200 earlyprintk";
};
memory {
device_type = "memory";
reg = <0 0x00000000 0 0x20000000>; /* 512 MB */
};
};
&L2 {
arm,parity-enable;
marvell,ecc-enable;
};
&devbus_bootcs {
status = "okay";
/* Device Bus parameters are required */
/* Read parameters */
devbus,bus-width = <16>;
devbus,turn-off-ps = <60000>;
devbus,badr-skew-ps = <0>;
devbus,acc-first-ps = <124000>;
devbus,acc-next-ps = <248000>;
devbus,rd-setup-ps = <0>;
devbus,rd-hold-ps = <0>;
/* Write parameters */
devbus,sync-enable = <0>;
devbus,wr-high-ps = <60000>;
devbus,wr-low-ps = <60000>;
devbus,ale-wr-ps = <60000>;
};
&uart0 {
status = "okay";
};
&uart1 {
status = "okay";
};
&i2c0 {
clock-frequency = <100000>;
status = "okay";
};
&usb0 {
status = "okay";
};
&spi0 {
status = "okay";
spi-flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "jedec,spi-nor";
reg = <0>; /* Chip select 0 */
spi-max-frequency = <108000000>;
m25p,fast-read;
partition@u-boot {
reg = <0x00000000 0x001f0000>;
label = "u-boot";
};
partition@u-boot-env {
reg = <0x001f0000 0x00010000>;
label = "u-boot-env";
};
partition@ubi1 {
reg = <0x00200000 0x00e00000>;
label = "ubi1";
};
};
};

20
arch/arm/boot/dts/aspeed-ast2600-evb.dts
View File

@@ -23,6 +23,15 @@
};
};
&mdio0 {
status = "okay";
ethphy0: ethernet-phy@0 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <0>;
};
};
&mdio1 {
status = "okay";
@@ -50,6 +59,17 @@
};
};
&mac0 {
status = "okay";
phy-mode = "rgmii";
phy-handle = <&ethphy0>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_rgmii1_default>;
};
&mac1 {
status = "okay";

77
arch/arm/boot/dts/aspeed-bmc-amd-ethanolx.dts
View File

@@ -13,6 +13,21 @@
memory@80000000 {
reg = <0x80000000 0x20000000>;
};
reserved-memory {
#address-cells = <1>;
#size-cells = <1>;
ranges;
video_engine_memory: jpegbuffer {
size = <0x02000000>; /* 32M */
alignment = <0x01000000>;
compatible = "shared-dma-pool";
reusable;
};
};
aliases {
serial0 = &uart1;
serial4 = &uart5;
@@ -82,6 +97,50 @@
&pinctrl_adc4_default>;
};
&gpio {
status = "okay";
gpio-line-names =
/*A0-A7*/ "","","FAULT_LED","CHASSIS_ID_LED","","","","",
/*B0-B7*/ "","","","","","","","",
/*C0-C7*/ "CHASSIS_ID_BTN","INTRUDER","AC_LOSS","","","","","",
/*D0-D7*/ "HDT_DBREQ","LOCAL_SPI_ROM_SEL","FPGA_SPI_ROM_SEL","JTAG_MUX_S",
"JTAG_MUX_OE","HDT_SEL","ASERT_WARM_RST_BTN","FPGA_RSVD",
/*E0-E7*/ "","","MON_P0_PWR_BTN","MON_P0_RST_BTN","MON_P0_NMI_BTN",
"MON_P0_PWR_GOOD","MON_PWROK","MON_RESET",
/*F0-F7*/ "MON_P0_PROCHOT","MON_P1_PROCHOT","MON_P0_THERMTRIP",
"MON_P1_THERMTRIP","P0_PRESENT","P1_PRESENT","MON_ATX_PWR_OK","",
/*G0-G7*/ "BRD_REV_ID_3","BRD_REV_ID_2","BRD_REV_ID_1","BRD_REV_ID_0",
"P0_APML_ALERT","P1_APML_ALERT","FPGA ALERT","",
/*H0-H7*/ "BRD_ID_0","BRD_ID_1","BRD_ID_2","BRD_ID_3",
"PCIE_DISCONNECTED","USB_DISCONNECTED","SPARE_0","SPARE_1",
/*I0-I7*/ "","","","","","","","",
/*J0-J7*/ "","","","","","","","",
/*K0-K7*/ "","","","","","","","",
/*L0-L7*/ "","","","","","","","",
/*M0-M7*/ "ASSERT_PWR_BTN","ASSERT_RST_BTN","ASSERT_NMI_BTN",
"ASSERT_LOCAL_LOCK","ASSERT_P0_PROCHOT","ASSERT_P1_PROCHOT",
"ASSERT_CLR_CMOS","ASSERT_BMC_READY",
/*N0-N7*/ "","","","","","","","",
/*O0-O7*/ "","","","","","","","",
/*P0-P7*/ "P0_VDD_CORE_RUN_VRHOT","P0_VDD_SOC_RUN_VRHOT",
"P0_VDD_MEM_ABCD_SUS_VRHOT","P0_VDD_MEM_EFGH_SUS_VRHOT",
"P1_VDD_CORE_RUN_VRHOT","P1_VDD_SOC_RUN_VRHOT",
"P1_VDD_MEM_ABCD_SUS_VRHOT","P1_VDD_MEM_EFGH_SUS_VRHOT",
/*Q0-Q7*/ "","","","","","","","",
/*R0-R7*/ "","","","","","","","",
/*S0-S7*/ "","","","","","","","",
/*T0-T7*/ "","","","","","","","",
/*U0-U7*/ "","","","","","","","",
/*V0-V7*/ "","","","","","","","",
/*W0-W7*/ "","","","","","","","",
/*X0-X7*/ "","","","","","","","",
/*Y0-Y7*/ "","","","","","","","",
/*Z0-Z7*/ "","","","","","","","",
/*AA0-AA7*/ "","SENSOR THERM","","","","","","",
/*AB0-AB7*/ "","","","","","","","",
/*AC0-AC7*/ "","","","","","","","";
};
//APML for P0
&i2c0 {
status = "okay";
@@ -139,17 +198,22 @@
&kcs1 {
status = "okay";
kcs_addr = <0x60>;
aspeed,lpc-io-reg = <0x60>;
};
&kcs2 {
status = "okay";
kcs_addr = <0x62>;
aspeed,lpc-io-reg = <0x62>;
};
&kcs3 {
status = "okay";
aspeed,lpc-io-reg = <0xCA2>;
};
&kcs4 {
status = "okay";
kcs_addr = <0x97DE>;
aspeed,lpc-io-reg = <0x97DE>;
};
&lpc_snoop {
@@ -215,5 +279,12 @@
};
};
&video {
status = "okay";
memory-region = <&video_engine_memory>;
};
&vhub {
status = "okay";
};

924
arch/arm/boot/dts/aspeed-bmc-bytedance-g220a.dts Normal file
View File

@@ -0,0 +1,924 @@
// SPDX-License-Identifier: GPL-2.0+
// Copyright (C) 2020 Bytedance.
/dts-v1/;
#include "aspeed-g5.dtsi"
#include <dt-bindings/gpio/aspeed-gpio.h>
#include <dt-bindings/i2c/i2c.h>
#include <dt-bindings/leds/leds-pca955x.h>
/ {
model = "Bytedance G220A BMC";
compatible = "bytedance,g220a-bmc", "aspeed,ast2500";
aliases {
serial4 = &uart5;
i2c14 = &channel_3_0;
i2c15 = &channel_3_1;
i2c16 = &channel_3_2;
i2c17 = &channel_3_3;
i2c18 = &channel_6_0;
i2c19 = &channel_6_1;
i2c20 = &channel_6_2;
i2c21 = &channel_6_3;
i2c22 = &channel_6_4;
i2c23 = &channel_6_5;
i2c24 = &channel_6_6;
i2c25 = &channel_6_7;
i2c26 = &channel_6_8;
i2c27 = &channel_6_9;
i2c28 = &channel_6_10;
i2c29 = &channel_6_11;
i2c30 = &channel_6_12;
i2c31 = &channel_6_13;
i2c32 = &channel_6_14;
i2c33 = &channel_6_15;
i2c34 = &channel_6_16;
i2c35 = &channel_6_17;
i2c36 = &channel_6_18;
i2c37 = &channel_6_19;
i2c38 = &channel_6_20;
i2c39 = &channel_6_21;
i2c40 = &channel_6_22;
i2c41 = &channel_6_23;
i2c42 = &channel_6_24;
i2c43 = &channel_6_25;
i2c44 = &channel_10_0;
i2c45 = &channel_10_1;
i2c46 = &channel_10_2;
i2c47 = &channel_10_3;
i2c48 = &channel_10_4;
i2c49 = &channel_10_5;
i2c50 = &channel_10_6;
i2c51 = &channel_10_7;
};
chosen {
stdout-path = &uart5;
bootargs = "console=ttyS4,115200 earlyprintk";
};
memory@80000000 {
reg = <0x80000000 0x40000000>;
};
reserved-memory {
#address-cells = <1>;
#size-cells = <1>;
ranges;
vga_memory: framebuffer@bc000000 {
no-map;
reg = <0xbc000000 0x04000000>; /* 64M */
};
video_engine_memory: jpegbuffer {
size = <0x02000000>; /* 32M */
alignment = <0x01000000>;
compatible = "shared-dma-pool";
reusable;
};
};
iio-hwmon {
compatible = "iio-hwmon";
io-channels = <&adc 0>, <&adc 1>, <&adc 2>, <&adc 3>,
<&adc 4>, <&adc 5>, <&adc 6>, <&adc 7>,
<&adc 8>, <&adc 9>, <&adc 10>, <&adc 11>,
<&adc 12>, <&adc 13>, <&adc 14>, <&adc 15>;
};
leds {
compatible = "gpio-leds";
bmc_alive {
label = "bmc_alive";
gpios = <&gpio ASPEED_GPIO(B, 0) GPIO_ACTIVE_LOW>;
linux,default-trigger = "timer";
led-pattern = <1000 1000>;
};
};
gpio-keys {
compatible = "gpio-keys";
burn-in-signal {
label = "burn-in";
gpios = <&gpio ASPEED_GPIO(R, 5) GPIO_ACTIVE_LOW>;
linux,code = <ASPEED_GPIO(R, 5)>;
};
};
gpio-keys-polled {
compatible = "gpio-keys-polled";
poll-interval = <1000>;
rear-riser1-presence {
label = "rear-riser1-presence";
gpios = <&pca0 1 GPIO_ACTIVE_LOW>;
linux,code = <1>;
};
alrt-pvddq-cpu0 {
label = "alrt-pvddq-cpu0";
gpios = <&pca0 8 GPIO_ACTIVE_LOW>;
linux,code = <2>;
};
rear-riser0-presence {
label = "rear-riser0-presence";
gpios = <&pca0 9 GPIO_ACTIVE_LOW>;
linux,code = <3>;
};
fault-pvddq-cpu0 {
label = "fault-pvddq-cpu0";
gpios = <&pca0 10 GPIO_ACTIVE_LOW>;
linux,code = <4>;
};
alrt-pvddq-cpu1 {
label = "alrt-pvddq-cpu1";
gpios = <&pca0 11 GPIO_ACTIVE_LOW>;
linux,code = <5>;
};
fault-pvddq-cpu1 {
label = "alrt-pvddq-cpu1";
gpios = <&pca0 12 GPIO_ACTIVE_LOW>;
linux,code = <6>;
};
fault-pvccin-cpu1 {
label = "fault-pvccin-cpuq";
gpios = <&pca0 13 GPIO_ACTIVE_LOW>;
linux,code = <7>;
};
bmc-rom0-wp {
label = "bmc-rom0-wp";
gpios = <&pca1 0 GPIO_ACTIVE_LOW>;
linux,code = <8>;
};
bmc-rom1-wp {
label = "bmc-rom1-wp";
gpios = <&pca1 1 GPIO_ACTIVE_LOW>;
linux,code = <9>;
};
fan0-presence {
label = "fan0-presence";
gpios = <&pca1 2 GPIO_ACTIVE_LOW>;
linux,code = <10>;
};
fan1-presence {
label = "fan1-presence";
gpios = <&pca1 3 GPIO_ACTIVE_LOW>;
linux,code = <11>;
};
fan2-presence {
label = "fan2-presence";
gpios = <&pca1 4 GPIO_ACTIVE_LOW>;
linux,code = <12>;
};
fan3-presence {
label = "fan3-presence";
gpios = <&pca1 5 GPIO_ACTIVE_LOW>;
linux,code = <13>;
};
fan4-presence {
label = "fan4-presence";
gpios = <&pca1 6 GPIO_ACTIVE_LOW>;
linux,code = <14>;
};
fan5-presence {
label = "fan5-presence";
gpios = <&pca1 7 GPIO_ACTIVE_LOW>;
linux,code = <15>;
};
front-bp1-presence {
label = "front-bp1-presence";
gpios = <&pca1 8 GPIO_ACTIVE_LOW>;
linux,code = <16>;
};
rear-bp-presence {
label = "rear-bp-presence";
gpios = <&pca1 9 GPIO_ACTIVE_LOW>;
linux,code = <17>;
};
fault-pvccin-cpu0 {
label = "fault-pvccin-cpu0";
gpios = <&pca1 10 GPIO_ACTIVE_LOW>;
linux,code = <18>;
};
alrt-p1v05-pvcc {
label = "alrt-p1v05-pvcc1";
gpios = <&pca1 11 GPIO_ACTIVE_LOW>;
linux,code = <19>;
};
fault-p1v05-pvccio {
label = "alrt-p1v05-pvcc1";
gpios = <&pca1 12 GPIO_ACTIVE_LOW>;
linux,code = <20>;
};
alrt-p1v8-pvccio {
label = "alrt-p1v8-pvccio";
gpios = <&pca1 13 GPIO_ACTIVE_LOW>;
linux,code = <21>;
};
fault-p1v8-pvccio {
label = "fault-p1v8-pvccio";
gpios = <&pca1 14 GPIO_ACTIVE_LOW>;
linux,code = <22>;
};
front-bp0-presence {
label = "front-bp0-presence";
gpios = <&pca1 15 GPIO_ACTIVE_LOW>;
linux,code = <23>;
};
};
};
&fmc {
status = "okay";
flash@0 {
status = "okay";
label = "bmc";
m25p,fast-read;
spi-max-frequency = <50000000>;
#include "openbmc-flash-layout-64.dtsi"
};
};
&spi1 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_spi1_default>;
flash@0 {
status = "okay";
m25p,fast-read;
label = "bios";
spi-max-frequency = <100000000>;
};
};
&adc {
status = "okay";
};
&gpio {
status = "okay";
gpio-line-names =
/*A0-A7*/ "SMRST_OCP_N","MAC2_LINK","BMC_CPLD_SMB_RST_R_N","BMC_CPLD_GPIO0",
"","","","",
/*B0-B7*/ "BMC_INIT_R_OK","FM_BOARD_REV_ID2","FM_PROJECT_ID7","FAULT_P12V_STBY_N",
"","CPU0_PROCHOT_LVT3_N","","BIOS_LOAD_DEFAULT_R_N",
/*C0-C7*/ "","","","","","","","",
/*D0-D7*/ "","","","","","","","",
/*E0-E7*/ "FM_PROJECT_ID0","FM_PROJECT_ID1","FM_PROJECT_ID2","FM_PROJECT_ID3",
"FM_PROJECT_ID4","FM_PROJECT_ID5","","",
/*F0-F7*/ "PSU0_PRSNT_N","PSU1_PRSNT_N","","FAULT_P12V_NVME_N",
"BIOS_DEBUG_MODE_R_N","DISABLE_CPU_DDR_R_SPD","COOLING_STRATEGY",
"PCH_GLB_RST_N",
/*G0-G7*/ "P12V_PMBUS_ALERT_N","CPLD_ALERT_N","BMC_RELOAD_N",
"P12V_PVDDQ_PMBUS_ALERT_N","BMC_JTAG_TCK_MUX_R_SEL","","NMI_OUT",
"NMI_BUTTON",
/*H0-H7*/ "BMC_CPLD_JTAG_TDI","BMC_CPLD_JTAG_TDO","BMC_CPLD_JTAG_TCK",
"BMC_CPLD_JTAG_TMS","FM_PROJECT_ID6","FM_BOARD_REV_ID0",
"PCA9546_U70_RST_N","IRQ_SML0_ALERT_N",
/*I0-I7*/ "FAULT_FRONT_RISER_P12V_N","FAULT_OCP_P12V_N","FM_BMC_PCH_SCI_R_N",
"","","","","",
/*J0-J7*/ "FM_CPU0_SKTOCC_N","FM_CPU1_SKTOCC_N","FM_CPU1_DISABLE_COD_N",
"","","","","",
/*K0-K7*/ "","","","","","","","",
/*L0-L7*/ "P12V_FAULT_N","PWRGD_P12V_PCIE_RISER","","LEAKAGE_DETECT_INPUT_N",
"","IRQ_SML1_PMBUS_ALERT_N","","",
/*M0-M7*/ "","","","","","","","",
/*N0-N7*/ "","","","","","","","",
/*O0-O7*/ "","","","","","","","",
/*P0-P7*/ "","","","","","","","",
/*Q0-Q7*/ "","","","","","","FM_PCH_THERMTRIP_N","CHASSIS_INTRUSION",
/*R0-R7*/ "","PVCCIN_CPU1_SMBALERT_N","BMC_PREQ_R_N","FAULT_P12V_PCIE_RISER_N",
"ALT_P12V_PCIE_RISER_N","BURN_BOARD_N","PVCCIN_CPU0_SMBALERT_N","",
/*S0-S7*/ "BMC_PRDY_N","SIO_POWER_GOOD","FM_BMC_PWR_DEBUG_R_N",
"FM_BMC_XDP_DEBUG_EN","","STRAP_BMC_BATTERY_GPIOS5","","",
/*T0-T7*/ "","","","","","","","",
/*U0-U7*/ "","","","","","","","",
/*V0-V7*/ "","","","","","","","",
/*W0-W7*/ "","","","","","","","",
/*X0-X7*/ "","","","","","","","",
/*Y0-Y7*/ "","PWRGD_PSU0_PWROK","CPU1_PROCHOT_LVT3_N","IRQ_BMC_PCH_SMI_LPC_N",
"","","","",
/*Z0-Z7*/ "XDP_PRSNT_N","BMC_XDP_SYS_PWROK","BMC_XDP_JTAG_SEL",
"PCH_BMC_SMI_ACTIVE_R_N","","","","",
/*AA0-AA7*/ "PWRGD_P12V_STBY_OCP","PS_PWROK","RST_PLTRST_BMC_R_N","HDA_SDO_R",
"FM_SLPS4_R_N","PWRGD_PSU1_PWROK","POWER_BUTTON","POWER_OUT",
/*AB0-AB7*/ "","RESET_OUT","SPI_BIOS_MODE_SELECT","POST_COMPLETE","","","","",
/*AC0-AC7*/ "","","","","","","","CPLD_PLTRST_B_N";
};
&kcs3 {
aspeed,lpc-io-reg = <0xCA2>;
status = "okay";
};
&kcs4 {
aspeed,lpc-io-reg = <0xCA4>;
status = "okay";
};
&lpc_snoop {
snoop-ports = <0x80>;
status = "okay";
};
&uart1 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_txd1_default
&pinctrl_rxd1_default
&pinctrl_nrts1_default
&pinctrl_ndtr1_default
&pinctrl_ndsr1_default
&pinctrl_ncts1_default
&pinctrl_ndcd1_default
&pinctrl_nri1_default>;
};
&uart2 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_txd2_default
&pinctrl_rxd2_default
&pinctrl_nrts2_default
&pinctrl_ndtr2_default
&pinctrl_ndsr2_default
&pinctrl_ncts2_default
&pinctrl_ndcd2_default
&pinctrl_nri2_default>;
};
&uart3 {
status = "okay";
};
&uart4 {
status = "okay";
};
&uart5 {
status = "okay";
};
&mac0 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_rmii1_default>;
clocks = <&syscon ASPEED_CLK_GATE_MAC1CLK>,
<&syscon ASPEED_CLK_MAC1RCLK>;
clock-names = "MACCLK", "RCLK";
use-ncsi;
};
&mac1 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_rgmii2_default &pinctrl_mdio2_default>;
};
&i2c0 {
status = "okay";
};
&i2c1 {
status = "okay";
};
&i2c2 {
status = "okay";
};
&i2c3 {
status = "okay";
i2c-switch@70 {
compatible = "nxp,pca9546";
reg = <0x70>;
#address-cells = <1>;
#size-cells = <0>;
channel_3_0: i2c@0 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0>;
};
channel_3_1: i2c@1 {
#address-cells = <1>;
#size-cells = <0>;
reg = <1>;
};
channel_3_2: i2c@2 {
#address-cells = <1>;
#size-cells = <0>;
reg = <2>;
};
channel_3_3: i2c@3 {
#address-cells = <1>;
#size-cells = <0>;
reg = <3>;
};
};
};
&i2c4 {
status = "okay";
};
&i2c5 {
status = "okay";
};
&i2c6 {
status = "okay";
i2c-switch@72 {
compatible = "nxp,pca9548";
reg = <0x72>;
#address-cells = <1>;
#size-cells = <0>;
channel_6_0: i2c@0 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0>;
};
channel_6_1: i2c@1 {
#address-cells = <1>;
#size-cells = <0>;
reg = <1>;
};
channel_6_2: i2c@2 {
#address-cells = <1>;
#size-cells = <0>;
reg = <2>;
};
channel_6_3: i2c@3 {
#address-cells = <1>;
#size-cells = <0>;
reg = <3>;
};
channel_6_4: i2c@4 {
#address-cells = <1>;
#size-cells = <0>;
reg = <4>;
};
channel_6_5: i2c@5 {
#address-cells = <1>;
#size-cells = <0>;
reg = <5>;
};
channel_6_6: i2c@6 {
#address-cells = <1>;
#size-cells = <0>;
reg = <6>;
};
channel_6_7: i2c@7 {
#address-cells = <1>;
#size-cells = <0>;
reg = <7>;
};
};
i2c-switch@70 {
compatible = "nxp,pca9546";
reg = <0x70>;
#address-cells = <1>;
#size-cells = <0>;
channel_6_8: i2c@0 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0>;
i2c-switch@71 {
compatible = "nxp,pca9546";
reg = <0x71>;
#address-cells = <1>;
#size-cells = <0>;
channel_6_12: i2c@0 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0>;
};
channel_6_13: i2c@1 {
#address-cells = <1>;
#size-cells = <0>;
reg = <1>;
};
channel_6_14: i2c@2 {
#address-cells = <1>;
#size-cells = <0>;
reg = <2>;
};
channel_6_15: i2c@3 {
#address-cells = <1>;
#size-cells = <0>;
reg = <3>;
};
};
};
channel_6_9: i2c@1 {
#address-cells = <1>;
#size-cells = <0>;
reg = <1>;
i2c-switch@71 {
compatible = "nxp,pca9546";
reg = <0x71>;
#address-cells = <1>;
#size-cells = <0>;
channel_6_16: i2c@0 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0>;
};
channel_6_17: i2c@1 {
#address-cells = <1>;
#size-cells = <0>;
reg = <1>;
};
channel_6_18: i2c@2 {
#address-cells = <1>;
#size-cells = <0>;
reg = <2>;
};
channel_6_19: i2c@3 {
#address-cells = <1>;
#size-cells = <0>;
reg = <3>;
};
};
};
channel_6_10: i2c@2 {
#address-cells = <1>;
#size-cells = <0>;
reg = <2>;
i2c-switch@71 {
compatible = "nxp,pca9546";
reg = <0x71>;
#address-cells = <1>;
#size-cells = <0>;
channel_6_20: i2c@0 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0>;
};
channel_6_21: i2c@1 {
#address-cells = <1>;
#size-cells = <0>;
reg = <1>;
};
channel_6_22: i2c@2 {
#address-cells = <1>;
#size-cells = <0>;
reg = <2>;
};
channel_6_23: i2c@3 {
#address-cells = <1>;
#size-cells = <0>;
reg = <3>;
};
};
};
channel_6_11: i2c@3 {
#address-cells = <1>;
#size-cells = <0>;
reg = <3>;
i2c-switch@71 {
compatible = "nxp,pca9546";
reg = <0x71>;
#address-cells = <1>;
#size-cells = <0>;
channel_6_24: i2c@0 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0>;
};
channel_6_25: i2c@1 {
#address-cells = <1>;
#size-cells = <0>;
reg = <1>;
};
};
};
};
};
&i2c7 {
status = "okay";
};
&i2c8 {
status = "okay";
pca0:pca9555@24 {
compatible = "nxp,pca9555";
reg = <0x24>;
#address-cells = <1>;
#size-cells = <0>;
gpio-controller;
#gpio-cells = <2>;
gpio@1 {
reg = <1>;
type = <PCA955X_TYPE_GPIO>;
};
gpio@8 {
reg = <8>;
type = <PCA955X_TYPE_GPIO>;
};
gpio@9 {
reg = <9>;
type = <PCA955X_TYPE_GPIO>;
};
gpio@10 {
reg = <10>;
type = <PCA955X_TYPE_GPIO>;
};
gpio@11 {
reg = <11>;
type = <PCA955X_TYPE_GPIO>;
};
gpio@12 {
reg = <12>;
type = <PCA955X_TYPE_GPIO>;
};
gpio@13 {
reg = <13>;
type = <PCA955X_TYPE_GPIO>;
};
};
pca1:pca9555@25 {
compatible = "nxp,pca9555";
reg = <0x25>;
#address-cells = <1>;
#size-cells = <0>;
gpio-controller;
#gpio-cells = <2>;
gpio@0 {
reg = <0>;
type = <PCA955X_TYPE_GPIO>;
};
gpio@1 {
reg = <1>;
type = <PCA955X_TYPE_GPIO>;
};
gpio@2 {
reg = <2>;
type = <PCA955X_TYPE_GPIO>;
};
gpio@3 {
reg = <3>;
type = <PCA955X_TYPE_GPIO>;
};
gpio@4 {
reg = <4>;
type = <PCA955X_TYPE_GPIO>;
};
gpio@5 {
reg = <5>;
type = <PCA955X_TYPE_GPIO>;
};
gpio@6 {
reg = <6>;
type = <PCA955X_TYPE_GPIO>;
};
gpio@7 {
reg = <7>;
type = <PCA955X_TYPE_GPIO>;
};
gpio@8 {
reg = <8>;
type = <PCA955X_TYPE_GPIO>;
};
gpio@9 {
reg = <9>;
type = <PCA955X_TYPE_GPIO>;
};
gpio@10 {
reg = <10>;
type = <PCA955X_TYPE_GPIO>;
};
gpio@11 {
reg = <11>;
type = <PCA955X_TYPE_GPIO>;
};
gpio@12 {
reg = <12>;
type = <PCA955X_TYPE_GPIO>;
};
gpio@13 {
reg = <13>;
type = <PCA955X_TYPE_GPIO>;
};
gpio@14 {
reg = <14>;
type = <PCA955X_TYPE_GPIO>;
};
gpio@15 {
reg = <15>;
type = <PCA955X_TYPE_GPIO>;
};
};
};
&i2c9 {
status = "okay";
};
&i2c10 {
status = "okay";
i2c-switch@70 {
compatible = "nxp,pca9546";
reg = <0x70>;
#address-cells = <1>;
#size-cells = <0>;
channel_10_0: i2c@0 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0>;
};
channel_10_1: i2c@1 {
#address-cells = <1>;
#size-cells = <0>;
reg = <1>;
};
channel_10_2: i2c@2 {
#address-cells = <1>;
#size-cells = <0>;
reg = <2>;
};
channel_10_3: i2c@3 {
#address-cells = <1>;
#size-cells = <0>;
reg = <3>;
};
};
i2c-switch@71 {
compatible = "nxp,pca9546";
reg = <0x71>;
#address-cells = <1>;
#size-cells = <0>;
channel_10_4: i2c@0 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0>;
};
channel_10_5: i2c@1 {
#address-cells = <1>;
#size-cells = <0>;
reg = <1>;
};
channel_10_6: i2c@2 {
#address-cells = <1>;
#size-cells = <0>;
reg = <2>;
};
channel_10_7: i2c@3 {
#address-cells = <1>;
#size-cells = <0>;
reg = <3>;
};
};
};
&i2c11 {
status = "okay";
};
&i2c12 {
status = "okay";
};
&i2c13 {
status = "okay";
};
&pwm_tacho {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm0_default &pinctrl_pwm1_default
&pinctrl_pwm2_default &pinctrl_pwm3_default
&pinctrl_pwm4_default &pinctrl_pwm5_default>;
fan@0 {
reg = <0x00>;
aspeed,fan-tach-ch = /bits/ 8 <0x00 0x01>;
};
fan@1 {
reg = <0x01>;
aspeed,fan-tach-ch = /bits/ 8 <0x02 0x03>;
};
fan@2 {
reg = <0x02>;
aspeed,fan-tach-ch = /bits/ 8 <0x04 0x05>;
};
fan@3 {
reg = <0x03>;
aspeed,fan-tach-ch = /bits/ 8 <0x06 0x07>;
};
fan@4 {
reg = <0x04>;
aspeed,fan-tach-ch = /bits/ 8 <0x08 0x09>;
};
fan@5 {
reg = <0x05>;
aspeed,fan-tach-ch = /bits/ 8 <0x0a 0x0b>;
};
};
&gpio {
pin_gpio_i3 {
gpio-hog;
gpios = <ASPEED_GPIO(I, 3) GPIO_ACTIVE_LOW>;
output-low;
line-name = "NCSI_BMC_R_SEL";
};
pin_gpio_b6 {
gpio-hog;
gpios = <ASPEED_GPIO(B, 6) GPIO_ACTIVE_LOW>;
output-low;
line-name = "EN_NCSI_SWITCH_N";
};
};
&video {
status = "okay";
memory-region = <&video_engine_memory>;
};
&vhub {
status = "okay";
};

57
arch/arm/boot/dts/aspeed-bmc-facebook-galaxy100.dts Normal file
View File

@@ -0,0 +1,57 @@
// SPDX-License-Identifier: GPL-2.0+
// Copyright (c) 2020 Facebook Inc.
/dts-v1/;
#include "ast2400-facebook-netbmc-common.dtsi"
/ {
model = "Facebook Galaxy 100 BMC";
compatible = "facebook,galaxy100-bmc", "aspeed,ast2400";
chosen {
stdout-path = &uart5;
bootargs = "console=ttyS0,9600n8 root=/dev/ram rw";
};
ast-adc-hwmon {
compatible = "iio-hwmon";
io-channels = <&adc 3>, <&adc 4>, <&adc 8>, <&adc 9>;
};
};
&wdt2 {
status = "okay";
aspeed,reset-type = "system";
};
&fmc {
flash@1 {
status = "okay";
m25p,fast-read;
label = "spi0.1";
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
flash1@0 {
reg = <0x0 0x2000000>;
label = "flash1";
};
};
};
};
&i2c9 {
status = "okay";
};
&vhub {
status = "okay";
};
&adc {
status = "okay";
};

888
arch/arm/boot/dts/aspeed-bmc-facebook-minipack.dts
View File

@@ -70,6 +70,162 @@
i2c45 = &imux45;
i2c46 = &imux46;
i2c47 = &imux47;
/*
* I2C Switch 24-0071 (channel #0 of 8-0070): 8 channels for
* connecting to left PDB (Power Distribution Board).
*/
i2c48 = &imux48;
i2c49 = &imux49;
i2c50 = &imux50;
i2c51 = &imux51;
i2c52 = &imux52;
i2c53 = &imux53;
i2c54 = &imux54;
i2c55 = &imux55;
/*
* I2C Switch 25-0072 (channel #1 of 8-0070): 8 channels for
* connecting to right PDB (Power Distribution Board).
*/
i2c56 = &imux56;
i2c57 = &imux57;
i2c58 = &imux58;
i2c59 = &imux59;
i2c60 = &imux60;
i2c61 = &imux61;
i2c62 = &imux62;
i2c63 = &imux63;
/*
* I2C Switch 26-0076 (channel #2 of 8-0070): 8 channels for
* connecting to top FCM (Fan Control Module).
*/
i2c64 = &imux64;
i2c65 = &imux65;
i2c66 = &imux66;
i2c67 = &imux67;
i2c68 = &imux68;
i2c69 = &imux69;
i2c70 = &imux70;
i2c71 = &imux71;
/*
* I2C Switch 27-0076 (channel #3 of 8-0070): 8 channels for
* connecting to bottom FCM (Fan Control Module).
*/
i2c72 = &imux72;
i2c73 = &imux73;
i2c74 = &imux74;
i2c75 = &imux75;
i2c76 = &imux76;
i2c77 = &imux77;
i2c78 = &imux78;
i2c79 = &imux79;
/*
* I2C Switch 40-0073 (channel #0 of 11-0070): connecting
* to PIM (Port Interface Module) #1 (1-based).
*/
i2c80 = &imux80;
i2c81 = &imux81;
i2c82 = &imux82;
i2c83 = &imux83;
i2c84 = &imux84;
i2c85 = &imux85;
i2c86 = &imux86;
i2c87 = &imux87;
/*
* I2C Switch 41-0073 (channel #1 of 11-0070): connecting
* to PIM (Port Interface Module) #2 (1-based).
*/
i2c88 = &imux88;
i2c89 = &imux89;
i2c90 = &imux90;
i2c91 = &imux91;
i2c92 = &imux92;
i2c93 = &imux93;
i2c94 = &imux94;
i2c95 = &imux95;
/*
* I2C Switch 42-0073 (channel #2 of 11-0070): connecting
* to PIM (Port Interface Module) #3 (1-based).
*/
i2c96 = &imux96;
i2c97 = &imux97;
i2c98 = &imux98;
i2c99 = &imux99;
i2c100 = &imux100;
i2c101 = &imux101;
i2c102 = &imux102;
i2c103 = &imux103;
/*
* I2C Switch 43-0073 (channel #3 of 11-0070): connecting
* to PIM (Port Interface Module) #4 (1-based).
*/
i2c104 = &imux104;
i2c105 = &imux105;
i2c106 = &imux106;
i2c107 = &imux107;
i2c108 = &imux108;
i2c109 = &imux109;
i2c110 = &imux110;
i2c111 = &imux111;
/*
* I2C Switch 44-0073 (channel #4 of 11-0070): connecting
* to PIM (Port Interface Module) #5 (1-based).
*/
i2c112 = &imux112;
i2c113 = &imux113;
i2c114 = &imux114;
i2c115 = &imux115;
i2c116 = &imux116;
i2c117 = &imux117;
i2c118 = &imux118;
i2c119 = &imux119;
/*
* I2C Switch 45-0073 (channel #5 of 11-0070): connecting
* to PIM (Port Interface Module) #6 (1-based).
*/
i2c120 = &imux120;
i2c121 = &imux121;
i2c122 = &imux122;
i2c123 = &imux123;
i2c124 = &imux124;
i2c125 = &imux125;
i2c126 = &imux126;
i2c127 = &imux127;
/*
* I2C Switch 46-0073 (channel #6 of 11-0070): connecting
* to PIM (Port Interface Module) #7 (1-based).
*/
i2c128 = &imux128;
i2c129 = &imux129;
i2c130 = &imux130;
i2c131 = &imux131;
i2c132 = &imux132;
i2c133 = &imux133;
i2c134 = &imux134;
i2c135 = &imux135;
/*
* I2C Switch 47-0073 (channel #7 of 11-0070): connecting
* to PIM (Port Interface Module) #8 (1-based).
*/
i2c136 = &imux136;
i2c137 = &imux137;
i2c138 = &imux138;
i2c139 = &imux139;
i2c140 = &imux140;
i2c141 = &imux141;
i2c142 = &imux142;
i2c143 = &imux143;
};
chosen {
@@ -184,11 +340,16 @@
&i2c2 {
status = "okay";
/*
* I2C Switch 2-0070 is connecting to SCM (System Controller
* Module).
*/
i2c-switch@70 {
compatible = "nxp,pca9548";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x70>;
i2c-mux-idle-disconnect;
imux16: i2c@0 {
#address-cells = <1>;
@@ -269,29 +430,270 @@
#address-cells = <1>;
#size-cells = <0>;
reg = <0x70>;
i2c-mux-idle-disconnect;
/*
* I2C Switch 8-0070 channel #0: connecting to left PDB
* (Power Distribution Board).
*/
imux24: i2c@0 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0>;
i2c-switch@71 {
compatible = "nxp,pca9548";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x71>;
i2c-mux-idle-disconnect;
imux48: i2c@0 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0>;
};
imux49: i2c@1 {
#address-cells = <1>;
#size-cells = <0>;
reg = <1>;
};
imux50: i2c@2 {
#address-cells = <1>;
#size-cells = <0>;
reg = <2>;
};
imux51: i2c@3 {
#address-cells = <1>;
#size-cells = <0>;
reg = <3>;
};
imux52: i2c@4 {
#address-cells = <1>;
#size-cells = <0>;
reg = <4>;
};
imux53: i2c@5 {
#address-cells = <1>;
#size-cells = <0>;
reg = <5>;
};
imux54: i2c@6 {
#address-cells = <1>;
#size-cells = <0>;
reg = <6>;
};
imux55: i2c@7 {
#address-cells = <1>;
#size-cells = <0>;
reg = <7>;
};
};
};
/*
* I2C Switch 8-0070 channel #1: connecting to right PDB
* (Power Distribution Board).
*/
imux25: i2c@1 {
#address-cells = <1>;
#size-cells = <0>;
reg = <1>;
i2c-switch@72 {
compatible = "nxp,pca9548";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x72>;
i2c-mux-idle-disconnect;
imux56: i2c@0 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0>;
};
imux57: i2c@1 {
#address-cells = <1>;
#size-cells = <0>;
reg = <1>;
};
imux58: i2c@2 {
#address-cells = <1>;
#size-cells = <0>;
reg = <2>;
};
imux59: i2c@3 {
#address-cells = <1>;
#size-cells = <0>;
reg = <3>;
};
imux60: i2c@4 {
#address-cells = <1>;
#size-cells = <0>;
reg = <4>;
};
imux61: i2c@5 {
#address-cells = <1>;
#size-cells = <0>;
reg = <5>;
};
imux62: i2c@6 {
#address-cells = <1>;
#size-cells = <0>;
reg = <6>;
};
imux63: i2c@7 {
#address-cells = <1>;
#size-cells = <0>;
reg = <7>;
};
};
};
/*
* I2C Switch 8-0070 channel #2: connecting to top FCM
* (Fan Control Module).
*/
imux26: i2c@2 {
#address-cells = <1>;
#size-cells = <0>;
reg = <2>;
i2c-switch@76 {
compatible = "nxp,pca9548";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x76>;
i2c-mux-idle-disconnect;
imux64: i2c@0 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0>;
};
imux65: i2c@1 {
#address-cells = <1>;
#size-cells = <0>;
reg = <1>;
};
imux66: i2c@2 {
#address-cells = <1>;
#size-cells = <0>;
reg = <2>;
};
imux67: i2c@3 {
#address-cells = <1>;
#size-cells = <0>;
reg = <3>;
};
imux68: i2c@4 {
#address-cells = <1>;
#size-cells = <0>;
reg = <4>;
};
imux69: i2c@5 {
#address-cells = <1>;
#size-cells = <0>;
reg = <5>;
};
imux70: i2c@6 {
#address-cells = <1>;
#size-cells = <0>;
reg = <6>;
};
imux71: i2c@7 {
#address-cells = <1>;
#size-cells = <0>;
reg = <7>;
};
};
};
/*
* I2C Switch 8-0070 channel #3: connecting to bottom
* FCM (Fan Control Module).
*/
imux27: i2c@3 {
#address-cells = <1>;
#size-cells = <0>;
reg = <3>;
i2c-switch@76 {
compatible = "nxp,pca9548";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x76>;
i2c-mux-idle-disconnect;
imux72: i2c@0 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0>;
};
imux73: i2c@1 {
#address-cells = <1>;
#size-cells = <0>;
reg = <1>;
};
imux74: i2c@2 {
#address-cells = <1>;
#size-cells = <0>;
reg = <2>;
};
imux75: i2c@3 {
#address-cells = <1>;
#size-cells = <0>;
reg = <3>;
};
imux76: i2c@4 {
#address-cells = <1>;
#size-cells = <0>;
reg = <4>;
};
imux77: i2c@5 {
#address-cells = <1>;
#size-cells = <0>;
reg = <5>;
};
imux78: i2c@6 {
#address-cells = <1>;
#size-cells = <0>;
reg = <6>;
};
imux79: i2c@7 {
#address-cells = <1>;
#size-cells = <0>;
reg = <7>;
};
};
};
imux28: i2c@4 {
@@ -323,11 +725,16 @@
&i2c9 {
status = "okay";
/*
* I2C Switch 9-0070 is connecting to MAC/PHY EEPROMs on SMB
* (Switch Main Board).
*/
i2c-switch@70 {
compatible = "nxp,pca9548";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x70>;
i2c-mux-idle-disconnect;
imux32: i2c@0 {
#address-cells = <1>;
@@ -391,53 +798,534 @@
#address-cells = <1>;
#size-cells = <0>;
reg = <0x70>;
i2c-mux-idle-disconnect;
/*
* I2C Switch 11-0070 channel #0: connecting to PIM
* (Port Interface Module) #1 (1-based).
*/
imux40: i2c@0 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0>;
i2c-switch@73 {
compatible = "nxp,pca9548";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x73>;
i2c-mux-idle-disconnect;
imux80: i2c@0 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0>;
};
imux81: i2c@1 {
#address-cells = <1>;
#size-cells = <0>;
reg = <1>;
};
imux82: i2c@2 {
#address-cells = <1>;
#size-cells = <0>;
reg = <2>;
};
imux83: i2c@3 {
#address-cells = <1>;
#size-cells = <0>;
reg = <3>;
};
imux84: i2c@4 {
#address-cells = <1>;
#size-cells = <0>;
reg = <4>;
};
imux85: i2c@5 {
#address-cells = <1>;
#size-cells = <0>;
reg = <5>;
};
imux86: i2c@6 {
#address-cells = <1>;
#size-cells = <0>;
reg = <6>;
};
imux87: i2c@7 {
#address-cells = <1>;
#size-cells = <0>;
reg = <7>;
};
};
};
/*
* I2C Switch 11-0070 channel #1: connecting to PIM
* (Port Interface Module) #2 (1-based).
*/
imux41: i2c@1 {
#address-cells = <1>;
#size-cells = <0>;
reg = <1>;
i2c-switch@73 {
compatible = "nxp,pca9548";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x73>;
i2c-mux-idle-disconnect;
imux88: i2c@0 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0>;
};
imux89: i2c@1 {
#address-cells = <1>;
#size-cells = <0>;
reg = <1>;
};
imux90: i2c@2 {
#address-cells = <1>;
#size-cells = <0>;
reg = <2>;
};
imux91: i2c@3 {
#address-cells = <1>;
#size-cells = <0>;
reg = <3>;
};
imux92: i2c@4 {
#address-cells = <1>;
#size-cells = <0>;
reg = <4>;
};
imux93: i2c@5 {
#address-cells = <1>;
#size-cells = <0>;
reg = <5>;
};
imux94: i2c@6 {
#address-cells = <1>;
#size-cells = <0>;
reg = <6>;
};
imux95: i2c@7 {
#address-cells = <1>;
#size-cells = <0>;
reg = <7>;
};
};
};
/*
* I2C Switch 11-0070 channel #2: connecting to PIM
* (Port Interface Module) #3 (1-based).
*/
imux42: i2c@2 {
#address-cells = <1>;
#size-cells = <0>;
reg = <2>;
i2c-switch@73 {
compatible = "nxp,pca9548";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x73>;
i2c-mux-idle-disconnect;
imux96: i2c@0 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0>;
};
imux97: i2c@1 {
#address-cells = <1>;
#size-cells = <0>;
reg = <1>;
};
imux98: i2c@2 {
#address-cells = <1>;
#size-cells = <0>;
reg = <2>;
};
imux99: i2c@3 {
#address-cells = <1>;
#size-cells = <0>;
reg = <3>;
};
imux100: i2c@4 {
#address-cells = <1>;
#size-cells = <0>;
reg = <4>;
};
imux101: i2c@5 {
#address-cells = <1>;
#size-cells = <0>;
reg = <5>;
};
imux102: i2c@6 {
#address-cells = <1>;
#size-cells = <0>;
reg = <6>;
};
imux103: i2c@7 {
#address-cells = <1>;
#size-cells = <0>;
reg = <7>;
};
};
};
/*
* I2C Switch 11-0070 channel #3: connecting to PIM
* (Port Interface Module) #4 (1-based).
*/
imux43: i2c@3 {
#address-cells = <1>;
#size-cells = <0>;
reg = <3>;
i2c-switch@73 {
compatible = "nxp,pca9548";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x73>;
i2c-mux-idle-disconnect;
imux104: i2c@0 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0>;
};
imux105: i2c@1 {
#address-cells = <1>;
#size-cells = <0>;
reg = <1>;
};
imux106: i2c@2 {
#address-cells = <1>;
#size-cells = <0>;
reg = <2>;
};
imux107: i2c@3 {
#address-cells = <1>;
#size-cells = <0>;
reg = <3>;
};
imux108: i2c@4 {
#address-cells = <1>;
#size-cells = <0>;
reg = <4>;
};
imux109: i2c@5 {
#address-cells = <1>;
#size-cells = <0>;
reg = <5>;
};
imux110: i2c@6 {
#address-cells = <1>;
#size-cells = <0>;
reg = <6>;
};
imux111: i2c@7 {
#address-cells = <1>;
#size-cells = <0>;
reg = <7>;
};
};
};
/*
* I2C Switch 11-0070 channel #4: connecting to PIM
* (Port Interface Module) #5 (1-based).
*/
imux44: i2c@4 {
#address-cells = <1>;
#size-cells = <0>;
reg = <4>;
i2c-switch@73 {
compatible = "nxp,pca9548";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x73>;
i2c-mux-idle-disconnect;
imux112: i2c@0 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0>;
};
imux113: i2c@1 {
#address-cells = <1>;
#size-cells = <0>;
reg = <1>;
};
imux114: i2c@2 {
#address-cells = <1>;
#size-cells = <0>;
reg = <2>;
};
imux115: i2c@3 {
#address-cells = <1>;
#size-cells = <0>;
reg = <3>;
};
imux116: i2c@4 {
#address-cells = <1>;
#size-cells = <0>;
reg = <4>;
};
imux117: i2c@5 {
#address-cells = <1>;
#size-cells = <0>;
reg = <5>;
};
imux118: i2c@6 {
#address-cells = <1>;
#size-cells = <0>;
reg = <6>;
};
imux119: i2c@7 {
#address-cells = <1>;
#size-cells = <0>;
reg = <7>;
};
};
};
/*
* I2C Switch 11-0070 channel #5: connecting to PIM
* (Port Interface Module) #6 (1-based).
*/
imux45: i2c@5 {
#address-cells = <1>;
#size-cells = <0>;
reg = <5>;
i2c-switch@73 {
compatible = "nxp,pca9548";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x73>;
i2c-mux-idle-disconnect;
imux120: i2c@0 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0>;
};
imux121: i2c@1 {
#address-cells = <1>;
#size-cells = <0>;
reg = <1>;
};
imux122: i2c@2 {
#address-cells = <1>;
#size-cells = <0>;
reg = <2>;
};
imux123: i2c@3 {
#address-cells = <1>;
#size-cells = <0>;
reg = <3>;
};
imux124: i2c@4 {
#address-cells = <1>;
#size-cells = <0>;
reg = <4>;
};
imux125: i2c@5 {
#address-cells = <1>;
#size-cells = <0>;
reg = <5>;
};
imux126: i2c@6 {
#address-cells = <1>;
#size-cells = <0>;
reg = <6>;
};
imux127: i2c@7 {
#address-cells = <1>;
#size-cells = <0>;
reg = <7>;
};
};
};
/*
* I2C Switch 11-0070 channel #6: connecting to PIM
* (Port Interface Module) #7 (1-based).
*/
imux46: i2c@6 {
#address-cells = <1>;
#size-cells = <0>;
reg = <6>;
i2c-switch@73 {
compatible = "nxp,pca9548";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x73>;
i2c-mux-idle-disconnect;
imux128: i2c@0 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0>;
};
imux129: i2c@1 {
#address-cells = <1>;
#size-cells = <0>;
reg = <1>;
};
imux130: i2c@2 {
#address-cells = <1>;
#size-cells = <0>;
reg = <2>;
};
imux131: i2c@3 {
#address-cells = <1>;
#size-cells = <0>;
reg = <3>;
};
imux132: i2c@4 {
#address-cells = <1>;
#size-cells = <0>;
reg = <4>;
};
imux133: i2c@5 {
#address-cells = <1>;
#size-cells = <0>;
reg = <5>;
};
imux134: i2c@6 {
#address-cells = <1>;
#size-cells = <0>;
reg = <6>;
};
imux135: i2c@7 {
#address-cells = <1>;
#size-cells = <0>;
reg = <7>;
};
};
};
/*
* I2C Switch 11-0070 channel #7: connecting to PIM
* (Port Interface Module) #8 (1-based).
*/
imux47: i2c@7 {
#address-cells = <1>;
#size-cells = <0>;
reg = <7>;
i2c-switch@73 {
compatible = "nxp,pca9548";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x73>;
i2c-mux-idle-disconnect;
imux136: i2c@0 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0>;
};
imux137: i2c@1 {
#address-cells = <1>;
#size-cells = <0>;
reg = <1>;
};
imux138: i2c@2 {
#address-cells = <1>;
#size-cells = <0>;
reg = <2>;
};
imux139: i2c@3 {
#address-cells = <1>;
#size-cells = <0>;
reg = <3>;
};
imux140: i2c@4 {
#address-cells = <1>;
#size-cells = <0>;
reg = <4>;
};
imux141: i2c@5 {
#address-cells = <1>;
#size-cells = <0>;
reg = <5>;
};
imux142: i2c@6 {
#address-cells = <1>;
#size-cells = <0>;
reg = <6>;
};
imux143: i2c@7 {
#address-cells = <1>;
#size-cells = <0>;
reg = <7>;
};
};
};
};
};

13
arch/arm/boot/dts/aspeed-bmc-facebook-tiogapass.dts
View File

@@ -82,11 +82,6 @@
status = "okay";
};
&vuart {
// VUART Host Console
status = "okay";
};
&uart1 {
// Host Console
status = "okay";
@@ -196,6 +191,14 @@
use-ncsi;
};
&mac1 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_rmii2_default>;
use-ncsi;
};
&adc {
status = "okay";
};

120
arch/arm/boot/dts/aspeed-bmc-facebook-wedge100.dts
View File

@@ -2,36 +2,16 @@
// Copyright (c) 2018 Facebook Inc.
/dts-v1/;
#include "aspeed-g4.dtsi"
#include "ast2400-facebook-netbmc-common.dtsi"
/ {
model = "Facebook Wedge 100 BMC";
compatible = "facebook,wedge100-bmc", "aspeed,ast2400";
aliases {
/*
* Override the default uart aliases to avoid breaking
* the legacy applications.
*/
serial0 = &uart5;
serial1 = &uart1;
serial2 = &uart3;
serial3 = &uart4;
};
chosen {
stdout-path = &uart3;
bootargs = "console=ttyS2,9600n8 root=/dev/ram rw";
};
memory@40000000 {
reg = <0x40000000 0x20000000>;
};
};
&wdt1 {
status = "okay";
aspeed,reset-type = "system";
};
&wdt2 {
@@ -40,108 +20,38 @@
};
&fmc {
status = "okay";
flash@0 {
flash@1 {
status = "okay";
m25p,fast-read;
label = "fmc0";
#include "facebook-bmc-flash-layout.dtsi"
label = "spi0.1";
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
flash1@0 {
reg = <0x0 0x2000000>;
label = "flash1";
};
};
};
};
&uart1 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_txd1_default
&pinctrl_rxd1_default>;
};
&uart3 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_txd3_default
&pinctrl_rxd3_default>;
};
&uart4 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_txd4_default
&pinctrl_rxd4_default>;
};
&uart5 {
status = "okay";
};
&mac1 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_rgmii2_default &pinctrl_mdio2_default>;
};
&i2c0 {
status = "okay";
};
&i2c1 {
status = "okay";
};
&i2c2 {
status = "okay";
};
&i2c3 {
status = "okay";
};
&i2c4 {
status = "okay";
};
&i2c5 {
status = "okay";
};
&i2c6 {
status = "okay";
};
&i2c7 {
status = "okay";
i2c-switch@70 {
compatible = "nxp,pca9548";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x70>;
i2c-mux-idle-disconnect;
};
};
&i2c8 {
status = "okay";
};
&i2c9 {
status = "okay";
};
&i2c10 {
status = "okay";
};
&i2c11 {
status = "okay";
};
&i2c12 {
status = "okay";
};
&i2c13 {
status = "okay";
};
&vhub {
status = "okay";

112
arch/arm/boot/dts/aspeed-bmc-facebook-wedge40.dts
View File

@@ -2,137 +2,27 @@
// Copyright (c) 2018 Facebook Inc.
/dts-v1/;
#include "aspeed-g4.dtsi"
#include "ast2400-facebook-netbmc-common.dtsi"
/ {
model = "Facebook Wedge 40 BMC";
compatible = "facebook,wedge40-bmc", "aspeed,ast2400";
aliases {
/*
* Override the default uart aliases to avoid breaking
* the legacy applications.
*/
serial0 = &uart5;
serial1 = &uart1;
serial2 = &uart3;
serial3 = &uart4;
};
chosen {
stdout-path = &uart3;
bootargs = "console=ttyS2,9600n8 root=/dev/ram rw";
};
memory@40000000 {
reg = <0x40000000 0x20000000>;
};
ast-adc-hwmon {
compatible = "iio-hwmon";
io-channels = <&adc 5>, <&adc 6>, <&adc 7>, <&adc 8>, <&adc 9>;
};
};
&wdt1 {
status = "okay";
aspeed,reset-type = "system";
};
&wdt2 {
status = "disabled";
};
&fmc {
status = "okay";
flash@0 {
status = "okay";
m25p,fast-read;
label = "spi0.0";
#include "facebook-bmc-flash-layout.dtsi"
};
};
&uart1 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_txd1_default
&pinctrl_rxd1_default>;
};
&uart3 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_txd3_default
&pinctrl_rxd3_default>;
};
&uart4 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_txd4_default
&pinctrl_rxd4_default
&pinctrl_ndts4_default>;
};
&uart5 {
status = "okay";
};
&mac1 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_rgmii2_default &pinctrl_mdio2_default>;
};
&i2c0 {
status = "okay";
};
&i2c1 {
status = "okay";
};
&i2c2 {
status = "okay";
};
&i2c3 {
status = "okay";
};
&i2c4 {
status = "okay";
};
&i2c5 {
status = "okay";
};
&i2c6 {
status = "okay";
};
&i2c7 {
status = "okay";
};
&i2c8 {
status = "okay";
};
&i2c11 {
status = "okay";
};
&i2c12 {
status = "okay";
};
&vhub {
status = "okay";
};
&adc {
status = "okay";
};

4
arch/arm/boot/dts/aspeed-bmc-facebook-wedge400.dts
View File

@@ -124,8 +124,8 @@
* "data0" partition (4MB) is reserved for persistent
* data store.
*/
data0@3800000 {
reg = <0x7c00000 0x800000>;
data0@7c00000 {
reg = <0x7c00000 0x400000>;
label = "data0";
};

37
arch/arm/boot/dts/aspeed-bmc-ibm-rainier-4u.dts Normal file
View File

@@ -0,0 +1,37 @@
// SPDX-License-Identifier: GPL-2.0-or-later
// Copyright 2020 IBM Corp.
/dts-v1/;
#include "aspeed-bmc-ibm-rainier.dts"
/ {
model = "Rainier 4U";
};
&i2c3 {
power-supply@6a {
compatible = "ibm,cffps";
reg = <0x6a>;
};
power-supply@6b {
compatible = "ibm,cffps";
reg = <0x6b>;
};
};
&fan0 {
tach-pulses = <4>;
};
&fan1 {
tach-pulses = <4>;
};
&fan2 {
tach-pulses = <4>;
};
&fan3 {
tach-pulses = <4>;
};

39
arch/arm/boot/dts/aspeed-bmc-ibm-rainier.dts
View File

@@ -8,7 +8,7 @@
#include <dt-bindings/leds/leds-pca955x.h>
/ {
model = "Rainier";
model = "Rainier 2U";
compatible = "ibm,rainier-bmc", "aspeed,ast2600";
aliases {
@@ -47,9 +47,18 @@
#size-cells = <1>;
ranges;
flash_memory: region@B8000000 {
flash_memory: region@b8000000 {
no-map;
reg = <0xB8000000 0x04000000>; /* 64M */
reg = <0xb8000000 0x04000000>; /* 64M */
};
ramoops@bc000000 {
compatible = "ramoops";
reg = <0xbc000000 0x180000>; /* 16 * (3 * 0x8000) */
record-size = <0x8000>;
console-size = <0x8000>;
pmsg-size = <0x8000>;
max-reason = <3>; /* KMSG_DUMP_EMERG */
};
vga_memory: region@bf000000 {
@@ -258,6 +267,7 @@
cfam0_spi2: spi@40 {
reg = <0x40>;
compatible = "ibm,fsi2spi-restricted";
#address-cells = <1>;
#size-cells = <0>;
@@ -274,6 +284,7 @@
cfam0_spi3: spi@60 {
reg = <0x60>;
compatible = "ibm,fsi2spi-restricted";
#address-cells = <1>;
#size-cells = <0>;
@@ -370,6 +381,7 @@
cfam1_spi2: spi@40 {
reg = <0x40>;
compatible = "ibm,fsi2spi-restricted";
#address-cells = <1>;
#size-cells = <0>;
@@ -386,6 +398,7 @@
cfam1_spi3: spi@60 {
reg = <0x60>;
compatible = "ibm,fsi2spi-restricted";
#address-cells = <1>;
#size-cells = <0>;
@@ -480,6 +493,7 @@
cfam2_spi2: spi@40 {
reg = <0x40>;
compatible = "ibm,fsi2spi-restricted";
#address-cells = <1>;
#size-cells = <0>;
@@ -496,6 +510,7 @@
cfam2_spi3: spi@60 {
reg = <0x60>;
compatible = "ibm,fsi2spi-restricted";
#address-cells = <1>;
#size-cells = <0>;
@@ -594,16 +609,6 @@
compatible = "ibm,cffps";
reg = <0x69>;
};
power-supply@6a {
compatible = "ibm,cffps";
reg = <0x6a>;
};
power-supply@6b {
compatible = "ibm,cffps";
reg = <0x6b>;
};
};
&i2c4 {
@@ -723,25 +728,25 @@
#address-cells = <1>;
#size-cells = <0>;
fan@0 {
fan0: fan@0 {
compatible = "pmbus-fan";
reg = <0>;
tach-pulses = <2>;
};
fan@1 {
fan1: fan@1 {
compatible = "pmbus-fan";
reg = <1>;
tach-pulses = <2>;
};
fan@2 {
fan2: fan@2 {
compatible = "pmbus-fan";
reg = <2>;
tach-pulses = <2>;
};
fan@3 {
fan3: fan@3 {
compatible = "pmbus-fan";
reg = <3>;
tach-pulses = <2>;

4
arch/arm/boot/dts/aspeed-bmc-intel-s2600wf.dts
View File

@@ -22,9 +22,9 @@
#size-cells = <1>;
ranges;
vga_memory: framebuffer@7f000000 {
vga_memory: framebuffer@9f000000 {
no-map;
reg = <0x7f000000 0x01000000>;
reg = <0x9f000000 0x01000000>; /* 16M */
};
};

11
arch/arm/boot/dts/aspeed-bmc-opp-tacoma.dts
View File

@@ -26,11 +26,20 @@
#size-cells = <1>;
ranges;
flash_memory: region@ba000000 {
flash_memory: region@b8000000 {
no-map;
reg = <0xb8000000 0x4000000>; /* 64M */
};
ramoops@bc000000 {
compatible = "ramoops";
reg = <0xbc000000 0x180000>; /* 16 * (3 * 0x8000) */
record-size = <0x8000>;
console-size = <0x8000>;
pmsg-size = <0x8000>;
max-reason = <3>; /* KMSG_DUMP_EMERG */
};
vga_memory: region@bf000000 {
no-map;
compatible = "shared-dma-pool";

2
arch/arm/boot/dts/aspeed-g6.dtsi
View File

@@ -363,7 +363,7 @@
#gpio-cells = <2>;
gpio-controller;
compatible = "aspeed,ast2600-gpio";
reg = <0x1e780000 0x800>;
reg = <0x1e780000 0x400>;
interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
gpio-ranges = <&pinctrl 0 0 208>;
ngpios = <208>;

117
arch/arm/boot/dts/ast2400-facebook-netbmc-common.dtsi Normal file
View File

@@ -0,0 +1,117 @@
// SPDX-License-Identifier: GPL-2.0+
// Copyright (c) 2020 Facebook Inc.
/dts-v1/;
#include "aspeed-g4.dtsi"
/ {
aliases {
/*
* Override the default uart aliases to avoid breaking
* the legacy applications.
*/
serial0 = &uart5;
serial1 = &uart1;
serial2 = &uart3;
serial3 = &uart4;
};
memory@40000000 {
reg = <0x40000000 0x20000000>;
};
};
&wdt1 {
status = "okay";
aspeed,reset-type = "system";
};
&fmc {
status = "okay";
flash@0 {
status = "okay";
m25p,fast-read;
label = "spi0.0";
#include "facebook-bmc-flash-layout.dtsi"
};
};
&uart1 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_txd1_default
&pinctrl_rxd1_default>;
};
&uart3 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_txd3_default
&pinctrl_rxd3_default>;
};
&uart4 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_txd4_default
&pinctrl_rxd4_default
&pinctrl_ndts4_default>;
};
&uart5 {
status = "okay";
};
&mac1 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_rgmii2_default &pinctrl_mdio2_default>;
};
&i2c0 {
status = "okay";
};
&i2c1 {
status = "okay";
};
&i2c2 {
status = "okay";
};
&i2c3 {
status = "okay";
};
&i2c4 {
status = "okay";
};
&i2c5 {
status = "okay";
};
&i2c6 {
status = "okay";
};
&i2c7 {
status = "okay";
};
&i2c8 {
status = "okay";
};
&i2c11 {
status = "okay";
};
&i2c12 {
status = "okay";
};
&vhub {
status = "okay";
};

55
arch/arm/boot/dts/at91-kizbox.dts
View File

@@ -48,48 +48,37 @@
};
};
pwm_leds {
led-controller {
compatible = "pwm-leds";
network_green {
led-1 {
label = "pwm:green:network";
pwms = <&tcb_pwm 2 10000000 PWM_POLARITY_INVERTED>;
pwms = <&tcb1_pwm1 0 10000000 PWM_POLARITY_INVERTED>;
max-brightness = <255>;
linux,default-trigger = "default-on";
};
network_red {
led-2 {
label = "pwm:red:network";
pwms = <&tcb_pwm 4 10000000 PWM_POLARITY_INVERTED>;
pwms = <&tcb1_pwm2 0 10000000 PWM_POLARITY_INVERTED>;
max-brightness = <255>;
linux,default-trigger = "default-on";
};
user_green {
led-3 {
label = "pwm:green:user";
pwms = <&tcb_pwm 0 10000000 PWM_POLARITY_INVERTED>;
pwms = <&tcb1_pwm0 0 10000000 PWM_POLARITY_INVERTED>;
max-brightness = <255>;
linux,default-trigger = "default-on";
};
user_red {
led-4 {
label = "pwm:red:user";
pwms = <&tcb_pwm 1 10000000 PWM_POLARITY_INVERTED>;
pwms = <&tcb1_pwm0 1 10000000 PWM_POLARITY_INVERTED>;
max-brightness = <255>;
linux,default-trigger = "default-on";
};
};
tcb_pwm: pwm {
compatible = "atmel,tcb-pwm";
#pwm-cells = <3>;
tc-block = <1>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_tcb1_tioa0
&pinctrl_tcb1_tioa1
&pinctrl_tcb1_tioa2
&pinctrl_tcb1_tiob0>;
};
};
&tcb0 {
@@ -104,6 +93,32 @@
};
};
&tcb1 {
tcb1_pwm0: pwm@0 {
compatible = "atmel,tcb-pwm";
reg = <0>;
#pwm-cells = <3>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_tcb1_tioa0 &pinctrl_tcb1_tiob0>;
};
tcb1_pwm1: pwm@1 {
compatible = "atmel,tcb-pwm";
reg = <1>;
#pwm-cells = <3>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_tcb1_tioa1>;
};
tcb1_pwm2: pwm@2 {
compatible = "atmel,tcb-pwm";
reg = <2>;
#pwm-cells = <3>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_tcb1_tioa2>;
};
};
&ebi {
status = "okay";
};

8
arch/arm/boot/dts/at91-kizbox2-common.dtsi
View File

@@ -58,24 +58,24 @@
};
};
pwm_leds {
led-controller {
compatible = "pwm-leds";
blue {
led-1 {
label = "pwm:blue:user";
pwms = <&pwm0 2 10000000 0>;
max-brightness = <255>;
linux,default-trigger = "none";
};
green {
led-2 {
label = "pwm:green:user";
pwms = <&pwm0 1 10000000 0>;
max-brightness = <255>;
linux,default-trigger = "default-on";
};
red {
led-3 {
label = "pwm:red:user";
pwms = <&pwm0 0 10000000 0>;
max-brightness = <255>;

16
arch/arm/boot/dts/at91-kizbox3-hs.dts
View File

@@ -15,40 +15,40 @@
model = "Overkiz KIZBOX3-HS";
compatible = "overkiz,kizbox3-hs", "atmel,sama5d2", "atmel,sama5";
pwm_leds {
led-controller-1 {
status = "okay";
red {
led-1 {
status = "okay";
};
green {
led-2 {
status = "okay";
};
blue {
led-3 {
status = "okay";
};
white {
led-4 {
status = "okay";
};
};
leds {
led-controller-2 {
compatible = "gpio-leds";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_led_red
&pinctrl_led_white>;
status = "okay";
red {
led-5 {
label = "pio:red:user";
gpios = <&pioA PIN_PB1 GPIO_ACTIVE_HIGH>;
default-state = "off";
};
white {
led-6 {
label = "pio:white:user";
gpios = <&pioA PIN_PB8 GPIO_ACTIVE_HIGH>;
default-state = "off";

10
arch/arm/boot/dts/at91-kizbox3_common.dtsi
View File

@@ -62,7 +62,7 @@
regulator-always-on;
};
pwm_leds {
led-controller-1 {
compatible = "pwm-leds";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm0_pwm_h0
@@ -71,7 +71,7 @@
&pinctrl_pwm0_pwm_h3>;
status = "disabled";
red {
led-1 {
label = "pwm:red:user";
pwms = <&pwm0 0 10000000 0>;
max-brightness = <255>;
@@ -79,7 +79,7 @@
status = "disabled";
};
green {
led-2 {
label = "pwm:green:user";
pwms = <&pwm0 1 10000000 0>;
max-brightness = <255>;
@@ -87,14 +87,14 @@
status = "disabled";
};
blue {
led-3 {
label = "pwm:blue:user";
pwms = <&pwm0 2 10000000 0>;
max-brightness = <255>;
status = "disabled";
};
white {
led-4 {
label = "pwm:white:user";
pwms = <&pwm0 3 10000000 0>;
max-brightness = <255>;

8
arch/arm/boot/dts/at91-kizboxmini-common.dtsi
View File

@@ -54,10 +54,10 @@
};
};
leds: pwm_leds {
leds: led-controller-1 {
compatible = "pwm-leds";
led_blue: pwm_blue {
led_blue: led-1 {
label = "pwm:blue:user";
pwms = <&pwm0 2 10000000 0>;
max-brightness = <255>;
@@ -65,14 +65,14 @@
status = "disabled";
};
led_green: pwm_green {
led_green: led-2 {
label = "pwm:green:user";
pwms = <&pwm0 0 10000000 0>;
max-brightness = <255>;
linux,default-trigger = "default-on";
};
led_red: pwm_red {
led_red: led-3 {
label = "pwm:red:user";
pwms = <&pwm0 1 10000000 0>;
max-brightness = <255>;

13
arch/arm/boot/dts/at91-sam9x60ek.dts
View File

@@ -569,11 +569,14 @@
atmel,pins = <AT91_PIOB 16 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>;
};
};
}; /* pinctrl */
&pmc {
atmel,osc-bypass;
};
usb1 {
pinctrl_usb_default: usb_default {
atmel,pins = <AT91_PIOD 15 AT91_PERIPH_GPIO AT91_PINCTRL_NONE
AT91_PIOD 16 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>;
};
};
}; /* pinctrl */
&pwm0 {
pinctrl-names = "default";
@@ -684,6 +687,8 @@
atmel,vbus-gpio = <0
&pioD 15 GPIO_ACTIVE_HIGH
&pioD 16 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb_default>;
status = "okay";
};

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