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media: rockchip: cif: fix rk356x dvp pclk polarity

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Signed-off-by: Allon Huang <allon.huang@rock-chips.com>
Change-Id: Ia5a41bf7b428c61d4b79911a88f9b93928de0ac6
Signed-off-by: Zefa Chen <zefa.chen@rock-chips.com>
This commit is contained in:
Allon Huang
2021-03-03 10:14:09 +08:00
committed by Zefa Chen
parent dd88cbecb3
commit 719446d5ff
1 changed files with 2 additions and 2 deletions
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4
drivers/media/platform/rockchip/cif/regs.h
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@@ -596,7 +596,7 @@ enum cif_reg_index {
#define CIF_SAMPLING_EDGE_SINGLE (0x01000000)
#define CIF_PCLK_DELAY_NUM(num) (0x00ff0000 | ((num) & 0xff))
#define CIF_GRF_VI_CON0 (0x340)
#define RK3568_CIF_PCLK_SAMPLING_EDGE_RISING (0x10001000)
#define RK3568_CIF_PCLK_SAMPLING_EDGE_FALLING (0x10000000)
#define RK3568_CIF_PCLK_SAMPLING_EDGE_RISING (0x10000000)
#define RK3568_CIF_PCLK_SAMPLING_EDGE_FALLING (0x10001000)
#endif