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arm64: dts: rockchip: rk3568: remove ddr_timing node

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Signed-off-by: YouMin Chen <cym@rock-chips.com>
Change-Id: Iaef7442a52bfadee989c507e4fb9e60d50f9c49e
This commit is contained in:
YouMin Chen
2021-09-30 20:15:52 +08:00
parent 6a53296ce8
commit 72edc8e464
2 changed files with 0 additions and 73 deletions
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72
arch/arm64/boot/dts/rockchip/rk3568-dram-default-timing.dtsi
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@@ -397,76 +397,4 @@
lp4_dq_vref_odtoff = <420>;
lp4_ca_vref_odtoff = <343>;
};
ddr_timing: ddr_timing {
compatible = "rockchip,ddr-timing";
ddr2_speed_bin = <DDR2_DEFAULT>;
ddr3_speed_bin = <DDR3_DEFAULT>;
ddr4_speed_bin = <DDR4_DEFAULT>;
pd_idle = <13>;
sr_idle = <93>;
sr_mc_gate_idle = <0>;
srpd_lite_idle = <0>;
standby_idle = <0>;
auto_pd_dis_freq = <1066>;
auto_sr_dis_freq = <800>;
ddr2_dll_dis_freq = <300>;
ddr3_dll_dis_freq = <300>;
ddr4_dll_dis_freq = <625>;
phy_dll_dis_freq = <400>;
ddr2_odt_dis_freq = <100>;
phy_ddr2_odt_dis_freq = <100>;
ddr2_drv = <DDR2_DS_REDUCE>;
ddr2_odt = <DDR2_ODT_150ohm>;
phy_ddr2_ca_drv = <PHY_DDR4_DS_ODT_DISABLE>;
phy_ddr2_ck_drv = <PHY_DDR4_DS_ODT_DISABLE>;
phy_ddr2_dq_drv = <PHY_DDR4_DS_ODT_DISABLE>;
phy_ddr2_odt = <PHY_DDR4_DS_ODT_DISABLE>;
ddr3_odt_dis_freq = <333>;
phy_ddr3_odt_dis_freq = <333>;
ddr3_drv = <DDR3_DS_34ohm>;
ddr3_odt = <DDR3_ODT_120ohm>;
phy_ddr3_ca_drv = <PHY_DDR4_DS_ODT_DISABLE>;
phy_ddr3_ck_drv = <PHY_DDR4_DS_ODT_DISABLE>;
phy_ddr3_dq_drv = <PHY_DDR4_DS_ODT_DISABLE>;
phy_ddr3_odt = <PHY_DDR4_DS_ODT_DISABLE>;
phy_lpddr2_odt_dis_freq = <333>;
lpddr2_drv = <LP2_DS_40ohm>;
phy_lpddr2_ca_drv = <PHY_DDR4_DS_ODT_DISABLE>;
phy_lpddr2_ck_drv = <PHY_DDR4_DS_ODT_DISABLE>;
phy_lpddr2_dq_drv = <PHY_DDR4_DS_ODT_DISABLE>;
phy_lpddr2_odt = <PHY_DDR4_DS_ODT_DISABLE>;
lpddr3_odt_dis_freq = <333>;
phy_lpddr3_odt_dis_freq = <333>;
lpddr3_drv = <LP3_DS_34ohm>;
lpddr3_odt = <LP3_ODT_120ohm>;
phy_lpddr3_ca_drv = <PHY_DDR4_DS_ODT_DISABLE>;
phy_lpddr3_ck_drv = <PHY_DDR4_DS_ODT_DISABLE>;
phy_lpddr3_dq_drv = <PHY_DDR4_DS_ODT_DISABLE>;
phy_lpddr3_odt = <PHY_DDR4_DS_ODT_DISABLE>;
lpddr4_odt_dis_freq = <333>;
phy_lpddr4_odt_dis_freq = <333>;
lpddr4_drv = <LP4_PDDS_40ohm>;
lpddr4_dq_odt = <LP4_DQ_ODT_240ohm>;
lpddr4_ca_odt = <LP4_CA_ODT_DIS>;
phy_lpddr4_ca_drv = <PHY_DDR4_DS_ODT_DISABLE>;
phy_lpddr4_ck_cs_drv = <PHY_DDR4_DS_ODT_DISABLE>;
phy_lpddr4_dq_drv = <PHY_DDR4_DS_ODT_DISABLE>;
phy_lpddr4_odt = <PHY_DDR4_DS_ODT_DISABLE>;
ddr4_odt_dis_freq = <625>;
phy_ddr4_odt_dis_freq = <625>;
ddr4_drv = <DDR4_DS_34ohm>;
ddr4_odt = <DDR4_ODT_120ohm>;
phy_ddr4_ca_drv = <PHY_DDR4_DS_ODT_DISABLE>;
phy_ddr4_ck_drv = <PHY_DDR4_DS_ODT_DISABLE>;
phy_ddr4_dq_drv = <PHY_DDR4_DS_ODT_DISABLE>;
phy_ddr4_odt = <PHY_DDR4_DS_ODT_DISABLE>;
};
};

1
arch/arm64/boot/dts/rockchip/rk3568.dtsi
View File

@@ -2150,7 +2150,6 @@
clocks = <&scmi_clk 3>;
clock-names = "dmc_clk";
operating-points-v2 = <&dmc_opp_table>;
ddr_timing = <&ddr_timing>;
vop-bw-dmc-freq = <
/* min_bw(MB/s) max_bw(MB/s) freq(KHz) */
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