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arm64: dts: rockchip: rk356x: adjust opp-table for correlation chips
1. limit vmin of cpu/gpu/npu/logic by mbist_vmin. 2. raise vdd_logic when npu run at 1.0GHz or venc run at 400MHz. 3. disable npu@1.0GHz and venc@400MHz by default. 4. reduce vdd_logic for the chips with big leakage. 5. adjust low-temp-adjust-volt table. Change-Id: If7ce6f010422d20e2dfd643a6894fa7304e6372f Signed-off-by: Liang Chen <cl@rock-chips.com>
This commit is contained in:
Liang Chen
@@ -34,6 +34,8 @@
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opp-1056000000 {
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opp-hz = /bits/ 64 <1056000000>;
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opp-microvolt = <900000>;
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opp-microvolt-L0 = <900000>;
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opp-microvolt-L1 = <850000>;
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};
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/delete-node/ opp-1560000000;
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};
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@@ -338,6 +338,12 @@
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};
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};
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&bus_npu {
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bus-supply = <&vdd_logic>;
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pvtm-supply = <&vdd_cpu>;
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status = "okay";
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};
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&can0 {
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assigned-clocks = <&cru CLK_CAN0>;
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assigned-clock-rates = <150000000>;
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@@ -1630,6 +1636,7 @@
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};
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&rkvenc {
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venc-supply = <&vdd_logic>;
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status = "okay";
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};
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@@ -132,16 +132,30 @@
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compatible = "operating-points-v2";
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opp-shared;
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mbist-vmin = <825000 900000 950000>;
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nvmem-cells = <&cpu_leakage>, <&core_pvtm>, <&mbist_vmin>;
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nvmem-cell-names = "leakage", "pvtm", "mbist-vmin";
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rockchip,pvtm-voltage-sel = <
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0 82000 0
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82001 93000 1
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93001 100000 2
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>;
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rockchip,pvtm-freq = <408000>;
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rockchip,pvtm-volt = <900000>;
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rockchip,pvtm-ch = <0 5>;
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rockchip,pvtm-sample-time = <1000>;
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rockchip,pvtm-number = <10>;
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rockchip,pvtm-error = <1000>;
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rockchip,pvtm-ref-temp = <40>;
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rockchip,pvtm-temp-prop = <26 26>;
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rockchip,thermal-zone = "soc-thermal";
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rockchip,temp-hysteresis = <5000>;
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rockchip,low-temp = <0>;
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rockchip,low-temp-adjust-volt = <
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/* MHz MHz uV */
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1104 1608 75000
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0 1608 75000
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>;
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nvmem-cells = <&cpu_leakage>;
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nvmem-cell-names = "leakage";
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opp-408000000 {
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opp-hz = /bits/ 64 <408000000>;
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opp-microvolt = <825000 825000 1150000>;
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@@ -1058,16 +1072,16 @@
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npu_opp_table: npu-opp-table {
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compatible = "operating-points-v2";
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mbist-vmin = <825000 900000 950000>;
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nvmem-cells = <&npu_leakage>, <&core_pvtm>, <&mbist_vmin>;
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nvmem-cell-names = "leakage", "pvtm", "mbist-vmin";
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rockchip,temp-hysteresis = <5000>;
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rockchip,low-temp = <0>;
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rockchip,low-temp-adjust-volt = <
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/* MHz MHz uV */
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700 700 50000
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0 700 50000
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>;
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nvmem-cells = <&npu_leakage>;
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nvmem-cell-names = "leakage";
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opp-200000000 {
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opp-hz = /bits/ 64 <200000000>;
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opp-microvolt = <825000 825000 1000000>;
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@@ -1099,6 +1113,42 @@
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opp-1000000000 {
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opp-hz = /bits/ 64 <1000000000>;
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opp-microvolt = <1000000 1000000 1000000>;
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status = "disabled";
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};
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};
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bus_npu: bus-npu {
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compatible = "rockchip,rk3568-bus";
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rockchip,busfreq-policy = "clkfreq";
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clocks = <&scmi_clk 2>;
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clock-names = "bus";
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operating-points-v2 = <&bus_npu_opp_table>;
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status = "disabled";
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};
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bus_npu_opp_table: bus-npu-opp-table {
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compatible = "operating-points-v2";
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opp-shared;
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nvmem-cells = <&core_pvtm>;
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nvmem-cell-names = "pvtm";
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rockchip,pvtm-voltage-sel = <
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0 82000 0
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82001 93000 1
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93001 100000 2
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>;
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rockchip,pvtm-ch = <0 5>;
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opp-1000000000 {
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opp-hz = /bits/ 64 <1000000000>;
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opp-microvolt = <950000>;
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opp-microvolt-L0 = <950000>;
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opp-microvolt-L1 = <925000>;
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opp-microvolt-L2 = <0>;
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};
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opp-900000000 {
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opp-hz = /bits/ 64 <900000000>;
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opp-microvolt = <0>;
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};
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};
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@@ -1147,8 +1197,9 @@
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gpu_opp_table: opp-table2 {
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compatible = "operating-points-v2";
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nvmem-cells = <&gpu_leakage>;
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nvmem-cell-names = "leakage";
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mbist-vmin = <825000 900000 950000>;
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nvmem-cells = <&gpu_leakage>, <&core_pvtm>, <&mbist_vmin>;
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nvmem-cell-names = "leakage", "pvtm", "mbist-vmin";
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opp-200000000 {
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opp-hz = /bits/ 64 <200000000>;
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@@ -1364,7 +1415,7 @@
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clocks = <&cru ACLK_RKVENC>, <&cru HCLK_RKVENC>,
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<&cru CLK_RKVENC_CORE>;
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clock-names = "aclk_vcodec", "hclk_vcodec", "clk_core";
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rockchip,normal-rates = <297000000>, <0>, <400000000>;
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rockchip,normal-rates = <297000000>, <0>, <297000000>;
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resets = <&cru SRST_A_RKVENC>, <&cru SRST_H_RKVENC>,
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<&cru SRST_RKVENC_CORE>;
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reset-names = "video_a", "video_h", "video_core";
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@@ -1376,9 +1427,38 @@
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rockchip,taskqueue-node = <3>;
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rockchip,resetgroup-node = <3>;
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power-domains = <&power RK3568_PD_RKVENC>;
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operating-points-v2 = <&rkvenc_opp_table>;
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status = "disabled";
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};
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rkvenc_opp_table: rkvenc-opp-table {
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compatible = "operating-points-v2";
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nvmem-cells = <&core_pvtm>;
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nvmem-cell-names = "pvtm";
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rockchip,pvtm-voltage-sel = <
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0 82000 0
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82001 93000 1
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93001 100000 2
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>;
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rockchip,pvtm-ch = <0 5>;
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opp-297000000 {
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opp-hz = /bits/ 64 <297000000>;
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opp-microvolt = <900000>;
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opp-microvolt-L0 = <900000>;
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opp-microvolt-L1 = <900000>;
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opp-microvolt-L2 = <850000>;
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};
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opp-400000000 {
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opp-hz = /bits/ 64 <400000000>;
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opp-microvolt = <950000>;
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opp-microvolt-L0 = <950000>;
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opp-microvolt-L1 = <900000>;
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opp-microvolt-L2 = <850000>;
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};
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};
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rkvenc_mmu: iommu@fdf40f00 {
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compatible = "rockchip,iommu-v2";
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reg = <0x0 0xfdf40f00 0x0 0x40>, <0x0 0xfdf40f40 0x0 0x40>;
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@@ -2053,33 +2133,50 @@
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dmc_opp_table: dmc-opp-table {
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compatible = "operating-points-v2";
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mbist-vmin = <825000 900000 950000>;
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nvmem-cells = <&log_leakage>, <&core_pvtm>, <&mbist_vmin>;
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nvmem-cell-names = "leakage", "pvtm", "mbist-vmin";
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rockchip,temp-hysteresis = <5000>;
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rockchip,low-temp = <0>;
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rockchip,low-temp-adjust-volt = <
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/* MHz MHz uV */
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0 1560 25000
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0 1560 25000
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>;
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rockchip,leakage-voltage-sel = <
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1 80 0
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81 254 1
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>;
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opp-324000000 {
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opp-hz = /bits/ 64 <324000000>;
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opp-microvolt = <900000>;
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opp-microvolt-L0 = <900000>;
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opp-microvolt-L1 = <850000>;
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};
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opp-528000000 {
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opp-hz = /bits/ 64 <528000000>;
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opp-microvolt = <900000>;
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opp-microvolt-L0 = <900000>;
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opp-microvolt-L1 = <850000>;
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};
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opp-780000000 {
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opp-hz = /bits/ 64 <780000000>;
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opp-microvolt = <900000>;
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opp-microvolt-L0 = <900000>;
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opp-microvolt-L1 = <850000>;
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};
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opp-920000000 {
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opp-hz = /bits/ 64 <920000000>;
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opp-microvolt = <900000>;
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opp-microvolt-L0 = <900000>;
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opp-microvolt-L1 = <850000>;
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status = "disabled";
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};
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opp-1560000000 {
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opp-hz = /bits/ 64 <1560000000>;
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opp-microvolt = <900000>;
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opp-microvolt-L0 = <900000>;
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opp-microvolt-L1 = <850000>;
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};
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};
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@@ -2396,6 +2493,10 @@
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reg = <0x08 0x1>;
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bits = <3 3>;
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};
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mbist_vmin: mbist-vmin@9 {
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reg = <0x09 0x1>;
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bits = <0 4>;
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};
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otp_id: id@a {
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reg = <0x0a 0x10>;
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};
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@@ -2411,6 +2512,9 @@
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gpu_leakage: gpu-leakage@1d {
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reg = <0x1d 0x1>;
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};
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core_pvtm:core-pvtm@2a {
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reg = <0x2a 0x2>;
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};
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};
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i2s0_8ch: i2s@fe400000 {
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