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clk: rockchip: rk3562: Fix clk_uart3_frac parent clk

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Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
Change-Id: Ief524953ddb3875ca1e99e63b99eca6193b7f3cc
This commit is contained in:
Finley Xiao
2023-11-08 12:02:18 +08:00
committed by Tao Huang
parent 04a82bed12
commit 776e251569
1 changed files with 1 additions and 1 deletions
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drivers/clk/rockchip/clk-rk3562.c
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@@ -624,7 +624,7 @@ static struct rockchip_clk_branch rk3562_clk_branches[] __initdata = {
COMPOSITE(CLK_UART3_SRC, "clk_uart3_src", gpll_cpll_p, 0,
RK3562_PERI_CLKSEL_CON(25), 8, 1, MFLAGS, 0, 7, DFLAGS,
RK3562_PERI_CLKGATE_CON(7), 15, GFLAGS),
COMPOSITE_FRACMUX(CLK_UART3_FRAC, "clk_uart3_frac", "clk_uart3", CLK_SET_RATE_PARENT,
COMPOSITE_FRACMUX(CLK_UART3_FRAC, "clk_uart3_frac", "clk_uart3_src", CLK_SET_RATE_PARENT,
RK3562_PERI_CLKSEL_CON(26), 0,
RK3562_PERI_CLKGATE_CON(8), 0, GFLAGS,
&rk3562_clk_uart3_fracmux),