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clk: rockchip: rk3368: fix NPLL with NB parameter types RK3066_PLL_RATE_NB

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with the NB parameter,can adjust the jitter of the output PLL.
make the npll jitter is better,make it more suitable for DCLK display.

Change-Id: I9d819bdc2b520205a7d63ee8ed83643601ccc821
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
This commit is contained in:
Elaine Zhang
2017-08-22 15:39:17 +08:00
committed by Huang, Tao
parent 4178a86547
commit 7b7167fa0f
1 changed files with 19 additions and 1 deletions
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20
drivers/clk/rockchip/clk-rk3368.c
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@@ -96,6 +96,24 @@ static struct rockchip_pll_rate_table rk3368_pll_rates[] = {
{ /* sentinel */ },
};
static struct rockchip_pll_rate_table rk3368_npll_rates[] = {
RK3066_PLL_RATE_NB(594000000, 1, 99, 4, 32),
RK3066_PLL_RATE_NB(585000000, 6, 585, 4, 32),
RK3066_PLL_RATE_NB(432000000, 3, 216, 4, 32),
RK3066_PLL_RATE_NB(426000000, 3, 213, 4, 32),
RK3066_PLL_RATE_NB(400000000, 1, 100, 6, 32),
RK3066_PLL_RATE_NB(342000000, 3, 171, 4, 32),
RK3066_PLL_RATE_NB(297000000, 2, 198, 8, 16),
RK3066_PLL_RATE_NB(270000000, 1, 135, 12, 32),
RK3066_PLL_RATE_NB(260000000, 1, 130, 12, 32),
RK3066_PLL_RATE_NB(148500000, 1, 99, 16, 32),
RK3066_PLL_RATE_NB(146250000, 6, 585, 16, 32),
RK3066_PLL_RATE_NB(108000000, 1, 54, 12, 32),
RK3066_PLL_RATE_NB(106500000, 4, 213, 12, 32),
RK3066_PLL_RATE_NB(85500000, 4, 171, 12, 32),
RK3066_PLL_RATE_NB(74250000, 4, 198, 16, 32),
};
PNAME(mux_pll_p) = { "xin24m", "xin32k" };
PNAME(mux_armclkb_p) = { "apllb_core", "gpllb_core" };
PNAME(mux_armclkl_p) = { "aplll_core", "gplll_core" };
@@ -148,7 +166,7 @@ static struct rockchip_pll_clock rk3368_pll_clks[] __initdata = {
[gpll] = PLL(pll_rk3066, PLL_GPLL, "gpll", mux_pll_p, 0, RK3368_PLL_CON(16),
RK3368_PLL_CON(19), 8, 4, ROCKCHIP_PLL_SYNC_RATE, rk3368_pll_rates),
[npll] = PLL(pll_rk3066, PLL_NPLL, "npll", mux_pll_p, 0, RK3368_PLL_CON(20),
RK3368_PLL_CON(23), 8, 5, 0, rk3368_pll_rates),
RK3368_PLL_CON(23), 8, 5, 0, rk3368_npll_rates),
};
static struct clk_div_table div_ddrphy_t[] = {