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drm/rockchip: bridge: analogix_dp: fix the regs settings for TEST_PATTERN_80BIT

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According to the DP PHY CTS v1.2b 3.2.3 and 3.3.3 chapters, the
PreEmphasis Level Test Pattern(PLTPAT), which also was called
80-bit custom pattern, should be:

1111100000 1111100000 1111100000 1111100000
1111100000 1111100000 1111100000 1111100000

It is used to verify the HBR2 in "Non Pre-Emphasis Level Verification
Testing" and "Pre-Emphasis Level Verification and Maximum Pk-Pk
Differential Voltage Testing".

Without this patch, the PLTPAT pattern is incorrect.

Fixes: 304dbb104d ("drm/bridge: analogix_dp: Add DP Test Automation")
Change-Id: I4b00acd0a360a8ba3f3eaf32fb30e0a18a451f5c
Signed-off-by: Damon Ding <damon.ding@rock-chips.com>
This commit is contained in:
Damon Ding
2024-12-19 09:50:57 +08:00
committed by DingLingsong
parent 7fdaaa54f6
commit 7bc0d73f22
1 changed files with 2 additions and 2 deletions
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4
drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
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@@ -738,9 +738,9 @@ void analogix_dp_set_training_pattern(struct analogix_dp_device *dp,
case TEST_PATTERN_80BIT:
reg = 0x3e0f83e0;
analogix_dp_write(dp, ANALOGIX_DP_TEST_80B_PATTERN0, reg);
reg = 0x0f83e0f8;
reg = 0x3e0f83e0;
analogix_dp_write(dp, ANALOGIX_DP_TEST_80B_PATTERN1, reg);
reg = 0x0000f83e;
reg = 0x000f83e0;
analogix_dp_write(dp, ANALOGIX_DP_TEST_80B_PATTERN2, reg);
reg = SCRAMBLING_ENABLE | LINK_QUAL_PATTERN_SET_80BIT;
analogix_dp_write(dp, ANALOGIX_DP_TRAINING_PTN_SET, reg);