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usb: dwc3: core: use 2.0 clk for 3.0 if only support 2.0 mode

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If the dwc3 core is programmed to operate in usb 2.0 only
mode, and no usb 3.0 phy, then it needs to set the bit
DEV_FORCE_20_CLK_FOR_30_CLK of GUCTL1 to make the internal
2.0(utmi/ulpi) clock to be routed as the 3.0 (pipe) clock.

Signed-off-by: William Wu <william.wu@rock-chips.com>
Signed-off-by: Bin Yang <yangbin@rock-chips.com>
Change-Id: I217a380815c21903c1090bd003c1d8ba2fadbe7c
This commit is contained in:
William Wu
2021-08-31 16:12:37 +08:00
parent 7e6d99ae56
commit 7e4881a49e
2 changed files with 5 additions and 0 deletions
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4
drivers/usb/dwc3/core.c
View File

@@ -1056,6 +1056,10 @@ static int dwc3_core_init(struct dwc3 *dwc)
if (dwc->parkmode_disable_ss_quirk)
reg |= DWC3_GUCTL1_PARKMODE_DISABLE_SS;
if (dwc->maximum_speed == USB_SPEED_HIGH ||
dwc->maximum_speed == USB_SPEED_FULL)
reg |= DWC3_GUCTL1_DEV_FORCE_20_CLK_FOR_30_CLK;
dwc3_writel(dwc->regs, DWC3_GUCTL1, reg);
}

1
drivers/usb/dwc3/core.h
View File

@@ -259,6 +259,7 @@
/* Global User Control 1 Register */
#define DWC3_GUCTL1_PARKMODE_DISABLE_SS BIT(17)
#define DWC3_GUCTL1_TX_IPGAP_LINECHECK_DIS BIT(28)
#define DWC3_GUCTL1_DEV_FORCE_20_CLK_FOR_30_CLK BIT(26)
#define DWC3_GUCTL1_DEV_L1_EXIT_BY_HW BIT(24)
/* Global Status Register */