shinys000114/linux
1
0
Fork 0
mirror of https://github.com/hardkernel/linux.git synced 2026-06-05 18:41:58 +09:00
Code Issues Packages Projects Releases Wiki Activity

misc: rk628: bt1120: fix read bt1120_dec clock frequency error

Browse Source 
Type: Fix
Redmine ID: N/A
Associated modifications: N/A
Test: N/A

Signed-off-by: Zhibin Huang <zhibin.huang@rock-chips.com>
Change-Id: I40f80f9d6a0daee6aedbae07cadfe24e7e171e56
This commit is contained in:
Zhibin Huang
2024-05-17 17:49:58 +08:00
parent 86b285adeb
commit 7e70102b91
2 changed files with 18 additions and 1 deletions
Download Patch File Download Diff File Expand all files Collapse all files

16
drivers/misc/rk628/rk628_cru.c
View File

@@ -480,6 +480,19 @@ static unsigned long rk628_cru_clk_set_rate_bt1120_dec(struct rk628 *rk628,
return parent_rate / div;
}
static unsigned long rk628_cru_clk_get_rate_bt1120_dec(struct rk628 *rk628)
{
unsigned long parent_rate;
u32 div;
parent_rate = rk628_cru_clk_get_rate_bt1120_dec_parent(rk628);
rk628_i2c_read(rk628, CRU_CLKSEL_CON02, &div);
div = (div & 0x1f) + 1;
return parent_rate / div;
}
int rk628_cru_clk_set_rate(struct rk628 *rk628, unsigned int id,
unsigned long rate)
{
@@ -536,6 +549,9 @@ unsigned long rk628_cru_clk_get_rate(struct rk628 *rk628, unsigned int id)
case CGU_CLK_HDMIRX_AUD:
rate = rk628_cru_clk_get_rate_sclk_hdmirx_aud(rk628);
break;
case CGU_BT1120DEC:
rate = rk628_cru_clk_get_rate_bt1120_dec(rk628);
break;
default:
return 0;
}

3
drivers/misc/rk628/rk628_rgb.c
View File

@@ -297,7 +297,8 @@ static void rk628_bt1120_decoder_enable(struct rk628 *rk628)
* so that the deviation between the actual clk and the required clk
* frequency is not significant.
*/
dec_clk_rate = rk628_cru_clk_set_rate(rk628, CGU_BT1120DEC, mode->clock * 1000);
rk628_cru_clk_set_rate(rk628, CGU_BT1120DEC, mode->clock * 1000);
dec_clk_rate = rk628_cru_clk_get_rate(rk628, CGU_BT1120DEC);
if (dec_clk_rate < mode->clock * 1000)
rk628_cru_clk_set_rate(rk628, CGU_BT1120DEC, mode->clock * 1020);