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usb: dwc3: rockchip: reduce the delay of controller reset

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The dwc3 controller gets clocks from the pipe_clk(125MHz),
utmi_clk(30MHz) and aclk(300MHz). It requires to wait several
clock cycles for the reset controller operation done. The
minimum clock is utmi_clk 30MHz, and suppose that 10 clock
cycles are required, it's about 0.33us. So delay 1us is enough.

Change-Id: I6980b92249356efc20c1f537aa3c83f91561cdd4
Signed-off-by: William Wu <william.wu@rock-chips.com>
This commit is contained in:
William Wu
2018-01-29 20:40:44 +08:00
committed by Tao Huang
parent 9cd51a5d78
commit 8177616add
1 changed files with 2 additions and 2 deletions
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4
drivers/usb/dwc3/dwc3-rockchip.c
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@@ -439,7 +439,7 @@ static void dwc3_rockchip_otg_extcon_evt_work(struct work_struct *work)
*/
if (!rockchip->skip_suspend) {
reset_control_assert(rockchip->otg_rst);
usleep_range(1000, 1200);
udelay(1);
reset_control_deassert(rockchip->otg_rst);
pm_runtime_get_sync(rockchip->dev);
@@ -487,7 +487,7 @@ static void dwc3_rockchip_otg_extcon_evt_work(struct work_struct *work)
* registers while the reset is asserted, with unknown impact.
*/
reset_control_assert(rockchip->otg_rst);
usleep_range(1000, 1200);
udelay(1);
reset_control_deassert(rockchip->otg_rst);
/*