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pinctrl: rockchip: remove gpiochip related codes
Remove gpiochip related codes from pinctrl driver, but populate gpio platform devices from device tree data. Change-Id: I347acaac2998a972e4c3be5c8827f77f468a7ad2 Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
This commit is contained in:
Jianqun Xu
@@ -47,56 +47,6 @@
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#include "core.h"
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#include "pinconf.h"
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struct rockchip_gpio_regs {
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u32 port_dr;
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u32 port_ddr;
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u32 int_en;
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u32 int_mask;
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u32 int_type;
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u32 int_polarity;
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u32 int_bothedge;
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u32 int_status;
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u32 int_rawstatus;
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u32 debounce;
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u32 dbclk_div_en;
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u32 dbclk_div_con;
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u32 port_eoi;
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u32 ext_port;
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u32 version_id;
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};
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static const struct rockchip_gpio_regs gpio_regs_v1 = {
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.port_dr = 0x00,
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.port_ddr = 0x04,
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.int_en = 0x30,
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.int_mask = 0x34,
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.int_type = 0x38,
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.int_polarity = 0x3c,
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.int_status = 0x40,
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.int_rawstatus = 0x44,
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.debounce = 0x48,
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.port_eoi = 0x4c,
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.ext_port = 0x50,
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};
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static const struct rockchip_gpio_regs gpio_regs_v2 = {
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.port_dr = 0x00,
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.port_ddr = 0x08,
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.int_en = 0x10,
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.int_mask = 0x18,
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.int_type = 0x20,
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.int_polarity = 0x28,
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.int_bothedge = 0x30,
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.int_status = 0x50,
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.int_rawstatus = 0x58,
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.debounce = 0x38,
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.dbclk_div_en = 0x40,
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.dbclk_div_con = 0x48,
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.port_eoi = 0x60,
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.ext_port = 0x70,
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.version_id = 0x78,
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};
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enum rockchip_pinctrl_type {
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PX30,
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RV1108,
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@@ -115,9 +65,6 @@ enum rockchip_pinctrl_type {
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#define RK_GENMASK_VAL(h, l, v) \
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(GENMASK(((h) + 16), ((l) + 16)) | (((v) << (l)) & GENMASK((h), (l))))
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#define GPIO_TYPE_V1 (0) /* GPIO Version ID reserved */
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#define GPIO_TYPE_V2 (0x01000C2B) /* GPIO Version ID 0x01000C2B */
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/**
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* Encode variants of iomux registers into a type variable
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*/
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@@ -519,81 +466,6 @@ static struct regmap_config rockchip_regmap_config = {
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.reg_stride = 4,
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};
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static inline void gpio_writel_v2(u32 val, void __iomem *reg)
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{
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writel((val & 0xffff) | 0xffff0000, reg);
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writel((val >> 16) | 0xffff0000, reg + 0x4);
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}
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static inline u32 gpio_readl_v2(void __iomem *reg)
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{
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return readl(reg + 0x4) << 16 | readl(reg);
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}
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static inline void rockchip_gpio_writel(struct rockchip_pin_bank *bank,
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u32 value, unsigned int offset)
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{
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void __iomem *reg = bank->reg_base + offset;
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if (bank->gpio_type == GPIO_TYPE_V2)
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gpio_writel_v2(value, reg);
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else
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writel(value, reg);
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}
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static inline u32 rockchip_gpio_readl(struct rockchip_pin_bank *bank,
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unsigned int offset)
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{
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void __iomem *reg = bank->reg_base + offset;
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u32 value;
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if (bank->gpio_type == GPIO_TYPE_V2)
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value = gpio_readl_v2(reg);
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else
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value = readl(reg);
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return value;
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}
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static inline void rockchip_gpio_writel_bit(struct rockchip_pin_bank *bank,
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u32 bit, u32 value,
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unsigned int offset)
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{
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void __iomem *reg = bank->reg_base + offset;
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u32 data;
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if (bank->gpio_type == GPIO_TYPE_V2) {
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if (value)
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data = BIT(bit % 16) | BIT(bit % 16 + 16);
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else
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data = BIT(bit % 16 + 16);
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writel(data, bit >= 16 ? reg + 0x4 : reg);
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} else {
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data = readl(reg);
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data &= ~BIT(bit);
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if (value)
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data |= BIT(bit);
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writel(data, reg);
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}
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}
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static inline u32 rockchip_gpio_readl_bit(struct rockchip_pin_bank *bank,
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u32 bit, unsigned int offset)
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{
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void __iomem *reg = bank->reg_base + offset;
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u32 data;
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if (bank->gpio_type == GPIO_TYPE_V2) {
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data = readl(bit >= 16 ? reg + 0x4 : reg);
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data >>= bit % 16;
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} else {
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data = readl(reg);
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data >>= bit;
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}
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return data & (0x1);
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}
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static inline const struct rockchip_pin_group *pinctrl_name_to_group(
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const struct rockchip_pinctrl *info,
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const char *name)
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@@ -1988,61 +1860,6 @@ rockchip_get_mux_route(struct rockchip_pin_bank *bank, int pin,
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return data->route_type;
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}
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static int rockchip_get_mux(struct rockchip_pin_bank *bank, int pin)
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{
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struct rockchip_pinctrl *info = bank->drvdata;
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int iomux_num = (pin / 8);
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struct regmap *regmap;
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unsigned int val;
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int reg, ret, mask, mux_type;
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u8 bit;
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if (iomux_num > 3)
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return -EINVAL;
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if (bank->iomux[iomux_num].type & IOMUX_UNROUTED) {
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dev_err(info->dev, "pin %d is unrouted\n", pin);
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return -EINVAL;
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}
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if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY)
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return RK_FUNC_GPIO;
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if (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU)
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regmap = info->regmap_pmu;
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else if (bank->iomux[iomux_num].type & IOMUX_L_SOURCE_PMU)
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regmap = (pin % 8 < 4) ? info->regmap_pmu : info->regmap_base;
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else
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regmap = info->regmap_base;
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/* get basic quadrupel of mux registers and the correct reg inside */
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mux_type = bank->iomux[iomux_num].type;
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reg = bank->iomux[iomux_num].offset;
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if (mux_type & IOMUX_WIDTH_4BIT) {
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if ((pin % 8) >= 4)
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reg += 0x4;
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bit = (pin % 4) * 4;
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mask = 0xf;
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} else if (mux_type & IOMUX_WIDTH_3BIT) {
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if ((pin % 8) >= 5)
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reg += 0x4;
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bit = (pin % 8 % 5) * 3;
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mask = 0x7;
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} else {
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bit = (pin % 8) * 2;
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mask = 0x3;
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}
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if (bank->recalced_mask & BIT(pin))
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rockchip_get_recalced_mux(bank, pin, ®, &bit, &mask);
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ret = regmap_read(regmap, reg, &val);
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if (ret)
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return ret;
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return ((val >> bit) & mask);
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}
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static int rockchip_verify_mux(struct rockchip_pin_bank *bank,
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int pin, int mux)
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{
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@@ -3426,72 +3243,11 @@ static int rockchip_pmx_set(struct pinctrl_dev *pctldev, unsigned selector,
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return 0;
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}
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static int rockchip_gpio_get_direction(struct gpio_chip *chip, unsigned offset)
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{
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struct rockchip_pin_bank *bank = gpiochip_get_data(chip);
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u32 data;
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data = rockchip_gpio_readl_bit(bank, offset, bank->gpio_regs->port_ddr);
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return !data;
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}
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/*
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* The calls to gpio_direction_output() and gpio_direction_input()
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* leads to this function call (via the pinctrl_gpio_direction_{input|output}()
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* function called from the gpiolib interface).
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*/
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static int _rockchip_pmx_gpio_set_direction(struct gpio_chip *chip,
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int pin, bool input)
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{
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struct rockchip_pin_bank *bank;
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int ret;
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unsigned long flags;
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bank = gpiochip_get_data(chip);
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ret = rockchip_set_mux(bank, pin, RK_FUNC_GPIO);
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if (ret < 0)
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return ret;
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raw_spin_lock_irqsave(&bank->slock, flags);
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/* set bit to 1 for output, 0 for input */
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rockchip_gpio_writel_bit(bank, pin, (u32)!input,
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bank->gpio_regs->port_ddr);
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raw_spin_unlock_irqrestore(&bank->slock, flags);
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return 0;
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}
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static int rockchip_pmx_gpio_set_direction(struct pinctrl_dev *pctldev,
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struct pinctrl_gpio_range *range,
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unsigned offset, bool input)
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{
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struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
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struct rockchip_pin_bank *bank = &info->ctrl->pin_banks[offset / 32];
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struct gpio_chip *chip;
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int pin;
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if (!bank || !bank->valid)
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return 0;
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chip = range->gc;
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pin = offset - chip->base;
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dev_dbg(info->dev, "gpio_direction for pin %u as %s-%d to %s\n",
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offset, range->name, pin, input ? "input" : "output");
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return _rockchip_pmx_gpio_set_direction(chip, offset - chip->base,
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input);
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}
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static const struct pinmux_ops rockchip_pmx_ops = {
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.get_functions_count = rockchip_pmx_get_funcs_count,
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.get_function_name = rockchip_pmx_get_func_name,
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.get_function_groups = rockchip_pmx_get_groups,
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.set_mux = rockchip_pmx_set,
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.gpio_set_direction = rockchip_pmx_gpio_set_direction,
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};
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/*
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@@ -3523,9 +3279,6 @@ static bool rockchip_pinconf_pull_valid(struct rockchip_pin_ctrl *ctrl,
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return false;
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}
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static void rockchip_gpio_set(struct gpio_chip *gc, unsigned offset, int value);
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static int rockchip_gpio_get(struct gpio_chip *gc, unsigned offset);
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/* set the pin config settings for a specified pin */
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static int rockchip_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
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unsigned long *configs, unsigned num_configs)
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@@ -3563,17 +3316,6 @@ static int rockchip_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
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if (rc)
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return rc;
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break;
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case PIN_CONFIG_OUTPUT:
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if (!bank->valid)
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return -ENOTSUPP;
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rockchip_gpio_set(&bank->gpio_chip,
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pin - bank->pin_base, arg);
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rc = _rockchip_pmx_gpio_set_direction(&bank->gpio_chip,
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pin - bank->pin_base, false);
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if (rc)
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return rc;
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break;
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case PIN_CONFIG_DRIVE_STRENGTH:
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/* rk3288 is the first with per-pin drive-strength */
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if (!info->ctrl->drv_calc_reg)
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@@ -3639,20 +3381,6 @@ static int rockchip_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin,
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arg = 1;
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break;
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case PIN_CONFIG_OUTPUT:
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if (!bank->valid)
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return -ENOTSUPP;
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rc = rockchip_get_mux(bank, pin - bank->pin_base);
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if (rc != RK_FUNC_GPIO)
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return -EINVAL;
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rc = rockchip_gpio_get(&bank->gpio_chip, pin - bank->pin_base);
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if (rc < 0)
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return rc;
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arg = rc ? 1 : 0;
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break;
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case PIN_CONFIG_DRIVE_STRENGTH:
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/* rk3288 is the first with per-pin drive-strength */
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if (!info->ctrl->drv_calc_reg)
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@@ -3930,564 +3658,6 @@ static int rockchip_pinctrl_register(struct platform_device *pdev,
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return 0;
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}
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/*
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* GPIO handling
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*/
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static void rockchip_gpio_set(struct gpio_chip *gc, unsigned offset, int value)
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{
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struct rockchip_pin_bank *bank = gpiochip_get_data(gc);
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unsigned long flags;
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raw_spin_lock_irqsave(&bank->slock, flags);
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rockchip_gpio_writel_bit(bank, offset, value, bank->gpio_regs->port_dr);
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raw_spin_unlock_irqrestore(&bank->slock, flags);
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}
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/*
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* Returns the level of the pin for input direction and setting of the DR
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* register for output gpios.
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*/
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static int rockchip_gpio_get(struct gpio_chip *gc, unsigned offset)
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{
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struct rockchip_pin_bank *bank = gpiochip_get_data(gc);
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u32 data;
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data = readl(bank->reg_base + bank->gpio_regs->ext_port);
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data >>= offset;
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data &= 1;
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return data;
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}
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/*
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* gpiolib gpio_direction_input callback function. The setting of the pin
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* mux function as 'gpio input' will be handled by the pinctrl subsystem
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* interface.
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*/
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static int rockchip_gpio_direction_input(struct gpio_chip *gc, unsigned offset)
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{
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return pinctrl_gpio_direction_input(gc->base + offset);
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}
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/*
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* gpiolib gpio_direction_output callback function. The setting of the pin
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* mux function as 'gpio output' will be handled by the pinctrl subsystem
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* interface.
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*/
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static int rockchip_gpio_direction_output(struct gpio_chip *gc,
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unsigned offset, int value)
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{
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rockchip_gpio_set(gc, offset, value);
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return pinctrl_gpio_direction_output(gc->base + offset);
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}
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static int rockchip_gpio_set_debounce(struct gpio_chip *gc,
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unsigned int offset, unsigned int debounce)
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{
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struct rockchip_pin_bank *bank = gpiochip_get_data(gc);
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const struct rockchip_gpio_regs *reg = bank->gpio_regs;
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unsigned long flags, div_reg, freq, max_debounce;
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bool div_debounce_support;
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unsigned int cur_div_reg;
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u64 div;
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if (!IS_ERR(bank->db_clk)) {
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div_debounce_support = true;
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freq = clk_get_rate(bank->db_clk);
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max_debounce = (GENMASK(23, 0) + 1) * 2 * 1000000 / freq;
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if (debounce > max_debounce)
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return -EINVAL;
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div = debounce * freq;
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div_reg = DIV_ROUND_CLOSEST_ULL(div, 2 * USEC_PER_SEC) - 1;
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} else {
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div_debounce_support = false;
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}
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raw_spin_lock_irqsave(&bank->slock, flags);
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/* Only the v1 needs to configure div_en and div_con for dbclk */
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if (debounce) {
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if (div_debounce_support) {
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/* Configure the max debounce from consumers */
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cur_div_reg = readl(bank->reg_base + reg->dbclk_div_con);
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if (cur_div_reg < div_reg)
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writel(div_reg, bank->reg_base + reg->dbclk_div_con);
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rockchip_gpio_writel_bit(bank, offset, 1,
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reg->dbclk_div_en);
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}
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rockchip_gpio_writel_bit(bank, offset, 1, reg->debounce);
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} else {
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if (div_debounce_support)
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rockchip_gpio_writel_bit(bank, offset, 0,
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reg->dbclk_div_en);
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rockchip_gpio_writel_bit(bank, offset, 0, reg->debounce);
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}
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||||
raw_spin_unlock_irqrestore(&bank->slock, flags);
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|
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/* Enable or disable dbclk at last */
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if (div_debounce_support) {
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if (debounce)
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clk_enable(bank->db_clk);
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else
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clk_disable(bank->db_clk);
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}
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return 0;
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}
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/*
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* gpiolib set_config callback function. The setting of the pin
|
||||
* mux function as 'gpio output' will be handled by the pinctrl subsystem
|
||||
* interface.
|
||||
*/
|
||||
static int rockchip_gpio_set_config(struct gpio_chip *gc, unsigned int offset,
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||||
unsigned long config)
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||||
{
|
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enum pin_config_param param = pinconf_to_config_param(config);
|
||||
unsigned int debounce = pinconf_to_config_argument(config);
|
||||
|
||||
switch (param) {
|
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case PIN_CONFIG_INPUT_DEBOUNCE:
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||||
rockchip_gpio_set_debounce(gc, offset, debounce);
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/*
|
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* Rockchip's gpio could only support up to one period
|
||||
* of the debounce clock(pclk), which is far away from
|
||||
* satisftying the requirement, as pclk is usually near
|
||||
* 100MHz shared by all peripherals. So the fact is it
|
||||
* has crippled debounce capability could only be useful
|
||||
* to prevent any spurious glitches from waking up the system
|
||||
* if the gpio is conguired as wakeup interrupt source. Let's
|
||||
* still return -ENOTSUPP as before, to make sure the caller
|
||||
* of gpiod_set_debounce won't change its behaviour.
|
||||
*/
|
||||
default:
|
||||
return -ENOTSUPP;
|
||||
}
|
||||
}
|
||||
|
||||
/*
|
||||
* gpiolib gpio_to_irq callback function. Creates a mapping between a GPIO pin
|
||||
* and a virtual IRQ, if not already present.
|
||||
*/
|
||||
static int rockchip_gpio_to_irq(struct gpio_chip *gc, unsigned offset)
|
||||
{
|
||||
struct rockchip_pin_bank *bank = gpiochip_get_data(gc);
|
||||
unsigned int virq;
|
||||
|
||||
if (!bank->domain)
|
||||
return -ENXIO;
|
||||
|
||||
virq = irq_create_mapping(bank->domain, offset);
|
||||
|
||||
return (virq) ? : -ENXIO;
|
||||
}
|
||||
|
||||
static const struct gpio_chip rockchip_gpiolib_chip = {
|
||||
.request = gpiochip_generic_request,
|
||||
.free = gpiochip_generic_free,
|
||||
.set = rockchip_gpio_set,
|
||||
.get = rockchip_gpio_get,
|
||||
.get_direction = rockchip_gpio_get_direction,
|
||||
.direction_input = rockchip_gpio_direction_input,
|
||||
.direction_output = rockchip_gpio_direction_output,
|
||||
.set_config = rockchip_gpio_set_config,
|
||||
.to_irq = rockchip_gpio_to_irq,
|
||||
.owner = THIS_MODULE,
|
||||
};
|
||||
|
||||
/*
|
||||
* Interrupt handling
|
||||
*/
|
||||
|
||||
static void rockchip_irq_demux(struct irq_desc *desc)
|
||||
{
|
||||
struct irq_chip *chip = irq_desc_get_chip(desc);
|
||||
struct rockchip_pin_bank *bank = irq_desc_get_handler_data(desc);
|
||||
const struct rockchip_gpio_regs *reg = bank->gpio_regs;
|
||||
u32 pend;
|
||||
|
||||
dev_dbg(bank->drvdata->dev, "got irq for bank %s\n", bank->name);
|
||||
|
||||
chained_irq_enter(chip, desc);
|
||||
|
||||
pend = readl_relaxed(bank->reg_base + reg->int_status);
|
||||
|
||||
while (pend) {
|
||||
unsigned int irq, virq;
|
||||
|
||||
irq = __ffs(pend);
|
||||
pend &= ~BIT(irq);
|
||||
virq = irq_find_mapping(bank->domain, irq);
|
||||
|
||||
if (!virq) {
|
||||
dev_err(bank->drvdata->dev, "unmapped irq %d\n", irq);
|
||||
continue;
|
||||
}
|
||||
|
||||
dev_dbg(bank->drvdata->dev, "handling irq %d\n", irq);
|
||||
|
||||
/*
|
||||
* Triggering IRQ on both rising and falling edge
|
||||
* needs manual intervention.
|
||||
*/
|
||||
if (bank->toggle_edge_mode & BIT(irq)) {
|
||||
u32 data, data_old, polarity;
|
||||
unsigned long flags;
|
||||
|
||||
data = readl_relaxed(bank->reg_base + reg->ext_port);
|
||||
do {
|
||||
raw_spin_lock_irqsave(&bank->slock, flags);
|
||||
|
||||
polarity = readl_relaxed(bank->reg_base +
|
||||
reg->int_polarity);
|
||||
if (data & BIT(irq))
|
||||
polarity &= ~BIT(irq);
|
||||
else
|
||||
polarity |= BIT(irq);
|
||||
writel(polarity, bank->reg_base +
|
||||
reg->int_polarity);
|
||||
|
||||
raw_spin_unlock_irqrestore(&bank->slock, flags);
|
||||
|
||||
data_old = data;
|
||||
data = readl_relaxed(bank->reg_base +
|
||||
reg->ext_port);
|
||||
} while ((data & BIT(irq)) != (data_old & BIT(irq)));
|
||||
}
|
||||
|
||||
generic_handle_irq(virq);
|
||||
}
|
||||
|
||||
chained_irq_exit(chip, desc);
|
||||
}
|
||||
|
||||
static int rockchip_irq_set_type(struct irq_data *d, unsigned int type)
|
||||
{
|
||||
struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
|
||||
struct rockchip_pin_bank *bank = gc->private;
|
||||
u32 mask = BIT(d->hwirq);
|
||||
u32 polarity;
|
||||
u32 level;
|
||||
u32 data;
|
||||
unsigned long flags;
|
||||
int ret;
|
||||
|
||||
/* make sure the pin is configured as gpio input */
|
||||
ret = rockchip_set_mux(bank, d->hwirq, RK_FUNC_GPIO);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
|
||||
raw_spin_lock_irqsave(&bank->slock, flags);
|
||||
|
||||
rockchip_gpio_writel_bit(bank, d->hwirq, 0,
|
||||
bank->gpio_regs->port_ddr);
|
||||
|
||||
raw_spin_unlock_irqrestore(&bank->slock, flags);
|
||||
|
||||
if (type & IRQ_TYPE_EDGE_BOTH)
|
||||
irq_set_handler_locked(d, handle_edge_irq);
|
||||
else
|
||||
irq_set_handler_locked(d, handle_level_irq);
|
||||
|
||||
raw_spin_lock_irqsave(&bank->slock, flags);
|
||||
irq_gc_lock(gc);
|
||||
|
||||
level = rockchip_gpio_readl(bank, bank->gpio_regs->int_type);
|
||||
polarity = rockchip_gpio_readl(bank, bank->gpio_regs->int_polarity);
|
||||
|
||||
switch (type) {
|
||||
case IRQ_TYPE_EDGE_BOTH:
|
||||
if (bank->gpio_type == GPIO_TYPE_V2) {
|
||||
bank->toggle_edge_mode &= ~mask;
|
||||
rockchip_gpio_writel_bit(bank, d->hwirq, 1,
|
||||
bank->gpio_regs->int_bothedge);
|
||||
irq_gc_unlock(gc);
|
||||
raw_spin_unlock_irqrestore(&bank->slock, flags);
|
||||
|
||||
return 0;
|
||||
} else {
|
||||
bank->toggle_edge_mode |= mask;
|
||||
level |= mask;
|
||||
|
||||
/*
|
||||
* Determine gpio state. If 1 next interrupt should be falling
|
||||
* otherwise rising.
|
||||
*/
|
||||
data = readl(bank->reg_base + bank->gpio_regs->ext_port);
|
||||
if (data & mask)
|
||||
polarity &= ~mask;
|
||||
else
|
||||
polarity |= mask;
|
||||
|
||||
break;
|
||||
}
|
||||
case IRQ_TYPE_EDGE_RISING:
|
||||
bank->toggle_edge_mode &= ~mask;
|
||||
level |= mask;
|
||||
polarity |= mask;
|
||||
break;
|
||||
case IRQ_TYPE_EDGE_FALLING:
|
||||
bank->toggle_edge_mode &= ~mask;
|
||||
level |= mask;
|
||||
polarity &= ~mask;
|
||||
break;
|
||||
case IRQ_TYPE_LEVEL_HIGH:
|
||||
bank->toggle_edge_mode &= ~mask;
|
||||
level &= ~mask;
|
||||
polarity |= mask;
|
||||
break;
|
||||
case IRQ_TYPE_LEVEL_LOW:
|
||||
bank->toggle_edge_mode &= ~mask;
|
||||
level &= ~mask;
|
||||
polarity &= ~mask;
|
||||
break;
|
||||
default:
|
||||
irq_gc_unlock(gc);
|
||||
raw_spin_unlock_irqrestore(&bank->slock, flags);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
rockchip_gpio_writel(bank, level, bank->gpio_regs->int_type);
|
||||
rockchip_gpio_writel(bank, polarity, bank->gpio_regs->int_polarity);
|
||||
|
||||
irq_gc_unlock(gc);
|
||||
raw_spin_unlock_irqrestore(&bank->slock, flags);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void rockchip_irq_suspend(struct irq_data *d)
|
||||
{
|
||||
struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
|
||||
struct rockchip_pin_bank *bank = gc->private;
|
||||
|
||||
bank->saved_masks = irq_reg_readl(gc, bank->gpio_regs->int_mask);
|
||||
irq_reg_writel(gc, ~gc->wake_active, bank->gpio_regs->int_mask);
|
||||
}
|
||||
|
||||
static void rockchip_irq_resume(struct irq_data *d)
|
||||
{
|
||||
struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
|
||||
struct rockchip_pin_bank *bank = gc->private;
|
||||
|
||||
irq_reg_writel(gc, bank->saved_masks, bank->gpio_regs->int_mask);
|
||||
}
|
||||
|
||||
static int rockchip_interrupts_register(struct platform_device *pdev,
|
||||
struct rockchip_pinctrl *info)
|
||||
{
|
||||
struct rockchip_pin_ctrl *ctrl = info->ctrl;
|
||||
struct rockchip_pin_bank *bank = ctrl->pin_banks;
|
||||
unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN;
|
||||
struct irq_chip_generic *gc;
|
||||
int ret;
|
||||
int i;
|
||||
|
||||
for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
|
||||
if (!bank->valid) {
|
||||
dev_warn(&pdev->dev, "bank %s is not valid\n",
|
||||
bank->name);
|
||||
continue;
|
||||
}
|
||||
|
||||
bank->domain = irq_domain_add_linear(bank->of_node, 32,
|
||||
&irq_generic_chip_ops, NULL);
|
||||
if (!bank->domain) {
|
||||
dev_warn(&pdev->dev, "could not initialize irq domain for bank %s\n",
|
||||
bank->name);
|
||||
continue;
|
||||
}
|
||||
|
||||
ret = irq_alloc_domain_generic_chips(bank->domain, 32, 1,
|
||||
bank->name, handle_level_irq,
|
||||
clr, 0, 0);
|
||||
if (ret) {
|
||||
dev_err(&pdev->dev, "could not alloc generic chips for bank %s\n",
|
||||
bank->name);
|
||||
irq_domain_remove(bank->domain);
|
||||
continue;
|
||||
}
|
||||
|
||||
gc = irq_get_domain_generic_chip(bank->domain, 0);
|
||||
if (bank->gpio_type == GPIO_TYPE_V2) {
|
||||
gc->reg_writel = gpio_writel_v2;
|
||||
gc->reg_readl = gpio_readl_v2;
|
||||
}
|
||||
gc->reg_base = bank->reg_base;
|
||||
gc->private = bank;
|
||||
gc->chip_types[0].regs.mask = bank->gpio_regs->int_mask;
|
||||
gc->chip_types[0].regs.ack = bank->gpio_regs->port_eoi;
|
||||
gc->chip_types[0].chip.irq_ack = irq_gc_ack_set_bit;
|
||||
gc->chip_types[0].chip.irq_mask = irq_gc_mask_set_bit;
|
||||
gc->chip_types[0].chip.irq_unmask = irq_gc_mask_clr_bit;
|
||||
gc->chip_types[0].chip.irq_enable = irq_gc_mask_clr_bit;
|
||||
gc->chip_types[0].chip.irq_disable = irq_gc_mask_set_bit;
|
||||
gc->chip_types[0].chip.irq_set_wake = irq_gc_set_wake;
|
||||
gc->chip_types[0].chip.irq_suspend = rockchip_irq_suspend;
|
||||
gc->chip_types[0].chip.irq_resume = rockchip_irq_resume;
|
||||
gc->chip_types[0].chip.irq_set_type = rockchip_irq_set_type;
|
||||
gc->wake_enabled = IRQ_MSK(bank->nr_pins);
|
||||
|
||||
/*
|
||||
* Linux assumes that all interrupts start out disabled/masked.
|
||||
* Our driver only uses the concept of masked and always keeps
|
||||
* things enabled, so for us that's all masked and all enabled.
|
||||
*/
|
||||
rockchip_gpio_writel(bank, 0xffffffff, bank->gpio_regs->int_mask);
|
||||
rockchip_gpio_writel(bank, 0xffffffff, bank->gpio_regs->int_en);
|
||||
gc->mask_cache = 0xffffffff;
|
||||
|
||||
irq_set_chained_handler_and_data(bank->irq,
|
||||
rockchip_irq_demux, bank);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int rockchip_gpiolib_register(struct platform_device *pdev,
|
||||
struct rockchip_pinctrl *info)
|
||||
{
|
||||
struct rockchip_pin_ctrl *ctrl = info->ctrl;
|
||||
struct rockchip_pin_bank *bank = ctrl->pin_banks;
|
||||
struct gpio_chip *gc;
|
||||
int ret;
|
||||
int i;
|
||||
|
||||
for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
|
||||
if (!bank->valid) {
|
||||
dev_warn(&pdev->dev, "bank %s is not valid\n",
|
||||
bank->name);
|
||||
continue;
|
||||
}
|
||||
|
||||
bank->gpio_chip = rockchip_gpiolib_chip;
|
||||
|
||||
gc = &bank->gpio_chip;
|
||||
gc->base = bank->pin_base;
|
||||
gc->ngpio = bank->nr_pins;
|
||||
gc->parent = &pdev->dev;
|
||||
gc->of_node = bank->of_node;
|
||||
gc->label = bank->name;
|
||||
|
||||
ret = gpiochip_add_data(gc, bank);
|
||||
if (ret) {
|
||||
dev_err(&pdev->dev, "failed to register gpio_chip %s, error code: %d\n",
|
||||
gc->label, ret);
|
||||
goto fail;
|
||||
}
|
||||
}
|
||||
|
||||
rockchip_interrupts_register(pdev, info);
|
||||
|
||||
return 0;
|
||||
|
||||
fail:
|
||||
for (--i, --bank; i >= 0; --i, --bank) {
|
||||
if (!bank->valid)
|
||||
continue;
|
||||
gpiochip_remove(&bank->gpio_chip);
|
||||
}
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int rockchip_gpiolib_unregister(struct platform_device *pdev,
|
||||
struct rockchip_pinctrl *info)
|
||||
{
|
||||
struct rockchip_pin_ctrl *ctrl = info->ctrl;
|
||||
struct rockchip_pin_bank *bank = ctrl->pin_banks;
|
||||
int i;
|
||||
|
||||
for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
|
||||
if (!bank->valid)
|
||||
continue;
|
||||
gpiochip_remove(&bank->gpio_chip);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int rockchip_get_bank_data(struct rockchip_pin_bank *bank,
|
||||
struct rockchip_pinctrl *info)
|
||||
{
|
||||
struct resource res;
|
||||
void __iomem *base;
|
||||
u32 ver_reg;
|
||||
|
||||
if (of_address_to_resource(bank->of_node, 0, &res)) {
|
||||
dev_err(info->dev, "cannot find IO resource for bank\n");
|
||||
return -ENOENT;
|
||||
}
|
||||
|
||||
bank->reg_base = devm_ioremap_resource(info->dev, &res);
|
||||
if (IS_ERR(bank->reg_base))
|
||||
return PTR_ERR(bank->reg_base);
|
||||
|
||||
/*
|
||||
* special case, where parts of the pull setting-registers are
|
||||
* part of the PMU register space
|
||||
*/
|
||||
if (of_device_is_compatible(bank->of_node,
|
||||
"rockchip,rk3188-gpio-bank0")) {
|
||||
struct device_node *node;
|
||||
|
||||
node = of_parse_phandle(bank->of_node->parent,
|
||||
"rockchip,pmu", 0);
|
||||
if (!node) {
|
||||
if (of_address_to_resource(bank->of_node, 1, &res)) {
|
||||
dev_err(info->dev, "cannot find IO resource for bank\n");
|
||||
return -ENOENT;
|
||||
}
|
||||
|
||||
base = devm_ioremap_resource(info->dev, &res);
|
||||
if (IS_ERR(base))
|
||||
return PTR_ERR(base);
|
||||
rockchip_regmap_config.max_register =
|
||||
resource_size(&res) - 4;
|
||||
rockchip_regmap_config.name =
|
||||
"rockchip,rk3188-gpio-bank0-pull";
|
||||
bank->regmap_pull = devm_regmap_init_mmio(info->dev,
|
||||
base,
|
||||
&rockchip_regmap_config);
|
||||
}
|
||||
}
|
||||
|
||||
bank->irq = irq_of_parse_and_map(bank->of_node, 0);
|
||||
|
||||
bank->clk = of_clk_get(bank->of_node, 0);
|
||||
if (IS_ERR(bank->clk)) {
|
||||
dev_err(info->dev, "cannot find clk\n");
|
||||
|
||||
return PTR_ERR(bank->clk);
|
||||
}
|
||||
|
||||
clk_prepare_enable(bank->clk);
|
||||
|
||||
/* If not gpio v2, that is default to v1. */
|
||||
ver_reg = gpio_regs_v2.version_id;
|
||||
if (readl(bank->reg_base + ver_reg) == GPIO_TYPE_V2) {
|
||||
bank->gpio_regs = &gpio_regs_v2;
|
||||
bank->gpio_type = GPIO_TYPE_V2;
|
||||
bank->db_clk = of_clk_get(bank->of_node, 1);
|
||||
if (IS_ERR(bank->db_clk)) {
|
||||
clk_disable_unprepare(bank->clk);
|
||||
dev_err(info->dev, "cannot find debounce clk\n");
|
||||
|
||||
return PTR_ERR(bank->db_clk);
|
||||
}
|
||||
|
||||
clk_prepare(bank->db_clk);
|
||||
} else {
|
||||
bank->gpio_regs = &gpio_regs_v1;
|
||||
bank->gpio_type = GPIO_TYPE_V1;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct of_device_id rockchip_pinctrl_dt_match[];
|
||||
|
||||
/* Ctrl data specially handle */
|
||||
@@ -4515,7 +3685,6 @@ static struct rockchip_pin_ctrl *rockchip_pinctrl_get_soc_data(
|
||||
{
|
||||
const struct of_device_id *match;
|
||||
struct device_node *node = pdev->dev.of_node;
|
||||
struct device_node *np;
|
||||
struct rockchip_pin_ctrl *ctrl;
|
||||
struct rockchip_pin_bank *bank;
|
||||
int grf_offs, pmu_offs, drv_grf_offs, drv_pmu_offs, i, j;
|
||||
@@ -4523,23 +3692,6 @@ static struct rockchip_pin_ctrl *rockchip_pinctrl_get_soc_data(
|
||||
match = of_match_node(rockchip_pinctrl_dt_match, node);
|
||||
ctrl = (struct rockchip_pin_ctrl *)match->data;
|
||||
|
||||
for_each_child_of_node(node, np) {
|
||||
if (!of_find_property(np, "gpio-controller", NULL))
|
||||
continue;
|
||||
|
||||
bank = ctrl->pin_banks;
|
||||
for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
|
||||
if (!strcmp(bank->name, np->name)) {
|
||||
bank->of_node = np;
|
||||
|
||||
if (!rockchip_get_bank_data(bank, d))
|
||||
bank->valid = true;
|
||||
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/* Ctrl data re-initialize for some Socs */
|
||||
if (ctrl->ctrl_data_re_init) {
|
||||
if (ctrl->ctrl_data_re_init(ctrl))
|
||||
@@ -4813,17 +3965,18 @@ static int rockchip_pinctrl_probe(struct platform_device *pdev)
|
||||
return ret;
|
||||
}
|
||||
|
||||
ret = rockchip_gpiolib_register(pdev, info);
|
||||
ret = rockchip_pinctrl_register(pdev, info);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
ret = rockchip_pinctrl_register(pdev, info);
|
||||
platform_set_drvdata(pdev, info);
|
||||
|
||||
ret = of_platform_populate(np, rockchip_bank_match, NULL, NULL);
|
||||
if (ret) {
|
||||
rockchip_gpiolib_unregister(pdev, info);
|
||||
dev_err(&pdev->dev, "failed to register gpio device\n");
|
||||
return ret;
|
||||
}
|
||||
|
||||
platform_set_drvdata(pdev, info);
|
||||
dev_info(dev, "probed %s\n", dev_name(dev));
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
Reference in New Issue
Block a user