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gpio: add gpio-rockchip driver
This gpio driver codes mostly are copied from pinctrl-rockchip.c with module fixes. Also it supports the old dt nodes. Change-Id: I7f26b5fe0827c16e2146a40e035a81de74284191 Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
This commit is contained in:
Jianqun Xu
@@ -438,6 +438,14 @@ config GPIO_REG
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A 32-bit single register GPIO fixed in/out implementation. This
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can be used to represent any register as a set of GPIO signals.
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config GPIO_ROCKCHIP
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tristate "Rockchip GPIO support"
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depends on ARCH_ROCKCHIP || COMPILE_TEST
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select GPIOLIB_IRQCHIP
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default ARCH_ROCKCHIP
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help
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Say yes here to support GPIO on Rockchip SoCs.
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config GPIO_SPEAR_SPICS
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bool "ST SPEAr13xx SPI Chip Select as GPIO support"
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depends on PLAT_SPEAR
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@@ -108,6 +108,7 @@ obj-$(CONFIG_GPIO_RC5T583) += gpio-rc5t583.o
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obj-$(CONFIG_GPIO_RDC321X) += gpio-rdc321x.o
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obj-$(CONFIG_GPIO_RCAR) += gpio-rcar.o
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obj-$(CONFIG_GPIO_REG) += gpio-reg.o
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obj-$(CONFIG_GPIO_ROCKCHIP) += gpio-rockchip.o
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obj-$(CONFIG_ARCH_SA1100) += gpio-sa1100.o
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obj-$(CONFIG_GPIO_SCH) += gpio-sch.o
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obj-$(CONFIG_GPIO_SCH311X) += gpio-sch311x.o
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775
drivers/gpio/gpio-rockchip.c
Normal file
775
drivers/gpio/gpio-rockchip.c
Normal file
@@ -0,0 +1,775 @@
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// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (c) 2020 Rockchip Electronics Co. Ltd.
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*
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*/
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#include <linux/init.h>
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#include <linux/module.h>
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#include <linux/bitops.h>
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#include <linux/clk.h>
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#include <linux/err.h>
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#include <linux/device.h>
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#include <linux/gpio/driver.h>
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/of_device.h>
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#include <linux/of_irq.h>
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#include <linux/regmap.h>
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#include "../pinctrl/core.h"
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#define GPIO_TYPE_V1 (0) /* GPIO Version ID reserved */
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#define GPIO_TYPE_V2 (0x01000C2B) /* GPIO Version ID 0x01000C2B */
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#define GPIO_BANK_PIN_NUM (32)
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struct rockchip_gpio_regs {
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u32 port_dr;
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u32 port_ddr;
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u32 int_en;
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u32 int_mask;
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u32 int_type;
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u32 int_polarity;
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u32 int_bothedge;
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u32 int_status;
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u32 int_rawstatus;
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u32 debounce;
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u32 dbclk_div_en;
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u32 dbclk_div_con;
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u32 port_eoi;
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u32 ext_port;
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u32 version_id;
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};
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static const struct rockchip_gpio_regs gpio_regs_v1 = {
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.port_dr = 0x00,
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.port_ddr = 0x04,
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.int_en = 0x30,
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.int_mask = 0x34,
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.int_type = 0x38,
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.int_polarity = 0x3c,
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.int_status = 0x40,
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.int_rawstatus = 0x44,
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.debounce = 0x48,
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.port_eoi = 0x4c,
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.ext_port = 0x50,
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};
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static const struct rockchip_gpio_regs gpio_regs_v2 = {
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.port_dr = 0x00,
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.port_ddr = 0x08,
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.int_en = 0x10,
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.int_mask = 0x18,
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.int_type = 0x20,
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.int_polarity = 0x28,
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.int_bothedge = 0x30,
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.int_status = 0x50,
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.int_rawstatus = 0x58,
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.debounce = 0x38,
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.dbclk_div_en = 0x40,
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.dbclk_div_con = 0x48,
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.port_eoi = 0x60,
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.ext_port = 0x70,
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.version_id = 0x78,
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};
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/**
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* @reg_base: register base of the gpio bank
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* @clk: clock of the gpio bank
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* @db_clk: clock of the gpio debounce
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* @irq: interrupt of the gpio bank
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* @saved_masks: Saved content of GPIO_INTEN at suspend time.
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* @pin_base: first pin number
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* @nr_pins: number of pins in this bank
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* @name: name of the bank
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* @of_node: dt node of this bank
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* @domain: irqdomain of the gpio bank
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* @gpio_chip: gpiolib chip
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* @slock: spinlock for the gpio bank
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*/
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struct rockchip_pin_bank {
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struct device *dev;
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void __iomem *reg_base;
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struct clk *clk;
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struct clk *db_clk;
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int irq;
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u32 saved_masks;
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u32 pin_base;
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u8 nr_pins;
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char *name;
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u32 gpio_type;
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struct device_node *of_node;
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struct irq_domain *domain;
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struct gpio_chip gpio_chip;
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raw_spinlock_t slock;
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const struct rockchip_gpio_regs *gpio_regs;
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u32 toggle_edge_mode;
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};
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static inline void gpio_writel_v2(u32 val, void __iomem *reg)
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{
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writel((val & 0xffff) | 0xffff0000, reg);
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writel((val >> 16) | 0xffff0000, reg + 0x4);
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}
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static inline u32 gpio_readl_v2(void __iomem *reg)
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{
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return readl(reg + 0x4) << 16 | readl(reg);
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}
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static inline void rockchip_gpio_writel(struct rockchip_pin_bank *bank,
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u32 value, unsigned int offset)
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{
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void __iomem *reg = bank->reg_base + offset;
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if (bank->gpio_type == GPIO_TYPE_V2)
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gpio_writel_v2(value, reg);
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else
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writel(value, reg);
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}
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static inline u32 rockchip_gpio_readl(struct rockchip_pin_bank *bank,
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unsigned int offset)
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{
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void __iomem *reg = bank->reg_base + offset;
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u32 value;
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if (bank->gpio_type == GPIO_TYPE_V2)
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value = gpio_readl_v2(reg);
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else
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value = readl(reg);
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return value;
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}
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static inline void rockchip_gpio_writel_bit(struct rockchip_pin_bank *bank,
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u32 bit, u32 value,
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unsigned int offset)
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{
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void __iomem *reg = bank->reg_base + offset;
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u32 data;
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if (bank->gpio_type == GPIO_TYPE_V2) {
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if (value)
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data = BIT(bit % 16) | BIT(bit % 16 + 16);
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else
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data = BIT(bit % 16 + 16);
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writel(data, bit >= 16 ? reg + 0x4 : reg);
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} else {
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data = readl(reg);
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data &= ~BIT(bit);
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if (value)
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data |= BIT(bit);
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writel(data, reg);
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}
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}
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static inline u32 rockchip_gpio_readl_bit(struct rockchip_pin_bank *bank,
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u32 bit, unsigned int offset)
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{
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void __iomem *reg = bank->reg_base + offset;
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u32 data;
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if (bank->gpio_type == GPIO_TYPE_V2) {
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data = readl(bit >= 16 ? reg + 0x4 : reg);
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data >>= bit % 16;
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} else {
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data = readl(reg);
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data >>= bit;
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}
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return data & (0x1);
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}
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static void rockchip_gpio_set(struct gpio_chip *gc, unsigned int offset, int value)
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{
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struct rockchip_pin_bank *bank = gpiochip_get_data(gc);
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unsigned long flags;
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raw_spin_lock_irqsave(&bank->slock, flags);
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rockchip_gpio_writel_bit(bank, offset, value, bank->gpio_regs->port_dr);
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raw_spin_unlock_irqrestore(&bank->slock, flags);
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}
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static int rockchip_gpio_get(struct gpio_chip *gc, unsigned int offset)
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{
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struct rockchip_pin_bank *bank = gpiochip_get_data(gc);
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u32 data;
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data = readl(bank->reg_base + bank->gpio_regs->ext_port);
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data >>= offset;
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data &= 1;
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return data;
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}
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static int rockchip_gpio_get_direction(struct gpio_chip *chip, unsigned int offset)
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{
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struct rockchip_pin_bank *bank = gpiochip_get_data(chip);
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u32 data;
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data = rockchip_gpio_readl_bit(bank, offset, bank->gpio_regs->port_ddr);
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return !data;
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}
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static int rockchip_gpio_set_direction(struct gpio_chip *chip, unsigned int offset, bool input)
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{
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struct rockchip_pin_bank *bank = gpiochip_get_data(chip);
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u32 data = input ? 0 : 1;
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rockchip_gpio_writel_bit(bank, offset, data, bank->gpio_regs->port_ddr);
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return 0;
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}
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static int rockchip_gpio_direction_input(struct gpio_chip *gc, unsigned int offset)
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{
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return rockchip_gpio_set_direction(gc, offset, true);
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}
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static int rockchip_gpio_direction_output(struct gpio_chip *gc,
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unsigned int offset, int value)
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{
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rockchip_gpio_set(gc, offset, value);
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return rockchip_gpio_set_direction(gc, offset, false);
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}
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static int rockchip_gpio_set_debounce(struct gpio_chip *gc,
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unsigned int offset, unsigned int debounce)
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{
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struct rockchip_pin_bank *bank = gpiochip_get_data(gc);
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const struct rockchip_gpio_regs *reg = bank->gpio_regs;
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unsigned long flags, div_reg, freq, max_debounce;
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bool div_debounce_support;
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unsigned int cur_div_reg;
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u64 div;
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if (!IS_ERR(bank->db_clk)) {
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div_debounce_support = true;
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freq = clk_get_rate(bank->db_clk);
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max_debounce = (GENMASK(23, 0) + 1) * 2 * 1000000 / freq;
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if (debounce > max_debounce)
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return -EINVAL;
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div = debounce * freq;
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div_reg = DIV_ROUND_CLOSEST_ULL(div, 2 * USEC_PER_SEC) - 1;
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} else {
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div_debounce_support = false;
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}
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raw_spin_lock_irqsave(&bank->slock, flags);
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/* Only the v1 needs to configure div_en and div_con for dbclk */
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if (debounce) {
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if (div_debounce_support) {
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/* Configure the max debounce from consumers */
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cur_div_reg = readl(bank->reg_base + reg->dbclk_div_con);
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if (cur_div_reg < div_reg)
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writel(div_reg, bank->reg_base + reg->dbclk_div_con);
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rockchip_gpio_writel_bit(bank, offset, 1,
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reg->dbclk_div_en);
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}
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rockchip_gpio_writel_bit(bank, offset, 1, reg->debounce);
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} else {
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if (div_debounce_support)
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rockchip_gpio_writel_bit(bank, offset, 0,
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reg->dbclk_div_en);
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rockchip_gpio_writel_bit(bank, offset, 0, reg->debounce);
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}
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raw_spin_unlock_irqrestore(&bank->slock, flags);
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/* Enable or disable dbclk at last */
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if (div_debounce_support) {
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if (debounce)
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clk_prepare_enable(bank->db_clk);
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else
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clk_disable_unprepare(bank->db_clk);
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}
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return 0;
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}
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/*
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* gpiolib set_config callback function. The setting of the pin
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* mux function as 'gpio output' will be handled by the pinctrl subsystem
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* interface.
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*/
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static int rockchip_gpio_set_config(struct gpio_chip *gc, unsigned int offset,
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unsigned long config)
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{
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enum pin_config_param param = pinconf_to_config_param(config);
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unsigned int debounce = pinconf_to_config_argument(config);
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int ret = 0;
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switch (param) {
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case PIN_CONFIG_INPUT_DEBOUNCE:
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/*
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* Rockchip's gpio could only support up to one period
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* of the debounce clock(pclk), which is far away from
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* satisftying the requirement, as pclk is usually near
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* 100MHz shared by all peripherals. So the fact is it
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* has crippled debounce capability could only be useful
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* to prevent any spurious glitches from waking up the system
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* if the gpio is conguired as wakeup interrupt source. Let's
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* still return -ENOTSUPP as before, to make sure the caller
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* of gpiod_set_debounce won't change its behaviour.
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*/
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rockchip_gpio_set_debounce(gc, offset, debounce);
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ret = -ENOTSUPP;
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break;
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default:
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ret = -ENOTSUPP;
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break;
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}
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return ret;
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}
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/*
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* gpiolib gpio_to_irq callback function. Creates a mapping between a GPIO pin
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* and a virtual IRQ, if not already present.
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*/
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static int rockchip_gpio_to_irq(struct gpio_chip *gc, unsigned int offset)
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{
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struct rockchip_pin_bank *bank = gpiochip_get_data(gc);
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unsigned int virq;
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if (!bank->domain)
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return -ENXIO;
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virq = irq_create_mapping(bank->domain, offset);
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return (virq) ? : -ENXIO;
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}
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static const struct gpio_chip rockchip_gpiolib_chip = {
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.request = gpiochip_generic_request,
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.free = gpiochip_generic_free,
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.set = rockchip_gpio_set,
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.get = rockchip_gpio_get,
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.get_direction = rockchip_gpio_get_direction,
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.direction_input = rockchip_gpio_direction_input,
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.direction_output = rockchip_gpio_direction_output,
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.set_config = rockchip_gpio_set_config,
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.to_irq = rockchip_gpio_to_irq,
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.owner = THIS_MODULE,
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};
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static void rockchip_irq_demux(struct irq_desc *desc)
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{
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struct irq_chip *chip = irq_desc_get_chip(desc);
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struct rockchip_pin_bank *bank = irq_desc_get_handler_data(desc);
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const struct rockchip_gpio_regs *reg = bank->gpio_regs;
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u32 pend;
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dev_dbg(bank->dev, "got irq for bank %s\n", bank->name);
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chained_irq_enter(chip, desc);
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pend = readl_relaxed(bank->reg_base + reg->int_status);
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while (pend) {
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unsigned int irq, virq;
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irq = __ffs(pend);
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pend &= ~BIT(irq);
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virq = irq_find_mapping(bank->domain, irq);
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if (!virq) {
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dev_err(bank->dev, "unmapped irq %d\n", irq);
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continue;
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}
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dev_dbg(bank->dev, "handling irq %d\n", irq);
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/*
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* Triggering IRQ on both rising and falling edge
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* needs manual intervention.
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*/
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if (bank->toggle_edge_mode & BIT(irq)) {
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u32 data, data_old, polarity;
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unsigned long flags;
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data = readl_relaxed(bank->reg_base + reg->ext_port);
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do {
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raw_spin_lock_irqsave(&bank->slock, flags);
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polarity = readl_relaxed(bank->reg_base +
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reg->int_polarity);
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if (data & BIT(irq))
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polarity &= ~BIT(irq);
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else
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polarity |= BIT(irq);
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writel(polarity, bank->reg_base +
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reg->int_polarity);
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raw_spin_unlock_irqrestore(&bank->slock, flags);
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data_old = data;
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data = readl_relaxed(bank->reg_base +
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reg->ext_port);
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} while ((data & BIT(irq)) != (data_old & BIT(irq)));
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}
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generic_handle_irq(virq);
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}
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chained_irq_exit(chip, desc);
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}
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static int rockchip_irq_set_type(struct irq_data *d, unsigned int type)
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{
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struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
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struct rockchip_pin_bank *bank = gc->private;
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u32 mask = BIT(d->hwirq);
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u32 polarity;
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u32 level;
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u32 data;
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unsigned long flags;
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int ret = 0;
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raw_spin_lock_irqsave(&bank->slock, flags);
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rockchip_gpio_writel_bit(bank, d->hwirq, 0,
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bank->gpio_regs->port_ddr);
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raw_spin_unlock_irqrestore(&bank->slock, flags);
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|
||||
if (type & IRQ_TYPE_EDGE_BOTH)
|
||||
irq_set_handler_locked(d, handle_edge_irq);
|
||||
else
|
||||
irq_set_handler_locked(d, handle_level_irq);
|
||||
|
||||
raw_spin_lock_irqsave(&bank->slock, flags);
|
||||
|
||||
level = rockchip_gpio_readl(bank, bank->gpio_regs->int_type);
|
||||
polarity = rockchip_gpio_readl(bank, bank->gpio_regs->int_polarity);
|
||||
|
||||
switch (type) {
|
||||
case IRQ_TYPE_EDGE_BOTH:
|
||||
if (bank->gpio_type == GPIO_TYPE_V2) {
|
||||
bank->toggle_edge_mode &= ~mask;
|
||||
rockchip_gpio_writel_bit(bank, d->hwirq, 1,
|
||||
bank->gpio_regs->int_bothedge);
|
||||
goto out;
|
||||
} else {
|
||||
bank->toggle_edge_mode |= mask;
|
||||
level |= mask;
|
||||
|
||||
/*
|
||||
* Determine gpio state. If 1 next interrupt should be falling
|
||||
* otherwise rising.
|
||||
*/
|
||||
data = readl(bank->reg_base + bank->gpio_regs->ext_port);
|
||||
if (data & mask)
|
||||
polarity &= ~mask;
|
||||
else
|
||||
polarity |= mask;
|
||||
}
|
||||
break;
|
||||
case IRQ_TYPE_EDGE_RISING:
|
||||
bank->toggle_edge_mode &= ~mask;
|
||||
level |= mask;
|
||||
polarity |= mask;
|
||||
break;
|
||||
case IRQ_TYPE_EDGE_FALLING:
|
||||
bank->toggle_edge_mode &= ~mask;
|
||||
level |= mask;
|
||||
polarity &= ~mask;
|
||||
break;
|
||||
case IRQ_TYPE_LEVEL_HIGH:
|
||||
bank->toggle_edge_mode &= ~mask;
|
||||
level &= ~mask;
|
||||
polarity |= mask;
|
||||
break;
|
||||
case IRQ_TYPE_LEVEL_LOW:
|
||||
bank->toggle_edge_mode &= ~mask;
|
||||
level &= ~mask;
|
||||
polarity &= ~mask;
|
||||
break;
|
||||
default:
|
||||
ret = -EINVAL;
|
||||
goto out;
|
||||
}
|
||||
|
||||
rockchip_gpio_writel(bank, level, bank->gpio_regs->int_type);
|
||||
rockchip_gpio_writel(bank, polarity, bank->gpio_regs->int_polarity);
|
||||
out:
|
||||
raw_spin_unlock_irqrestore(&bank->slock, flags);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static void rockchip_irq_suspend(struct irq_data *d)
|
||||
{
|
||||
struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
|
||||
struct rockchip_pin_bank *bank = gc->private;
|
||||
|
||||
bank->saved_masks = irq_reg_readl(gc, bank->gpio_regs->int_mask);
|
||||
irq_reg_writel(gc, ~gc->wake_active, bank->gpio_regs->int_mask);
|
||||
}
|
||||
|
||||
static void rockchip_irq_resume(struct irq_data *d)
|
||||
{
|
||||
struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
|
||||
struct rockchip_pin_bank *bank = gc->private;
|
||||
|
||||
irq_reg_writel(gc, bank->saved_masks, bank->gpio_regs->int_mask);
|
||||
}
|
||||
|
||||
static int rockchip_interrupts_register(struct rockchip_pin_bank *bank)
|
||||
{
|
||||
unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN;
|
||||
struct irq_chip_generic *gc;
|
||||
int ret;
|
||||
|
||||
bank->domain = irq_domain_add_linear(bank->of_node, 32,
|
||||
&irq_generic_chip_ops, NULL);
|
||||
if (!bank->domain) {
|
||||
dev_warn(bank->dev, "could not initialize irq domain for bank %s\n", bank->name);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
ret = irq_alloc_domain_generic_chips(bank->domain, 32, 1,
|
||||
bank->name, handle_level_irq,
|
||||
clr, 0, 0);
|
||||
if (ret) {
|
||||
dev_err(bank->dev, "could not alloc generic chips for bank %s\n", bank->name);
|
||||
irq_domain_remove(bank->domain);
|
||||
return ret;
|
||||
}
|
||||
|
||||
gc = irq_get_domain_generic_chip(bank->domain, 0);
|
||||
if (bank->gpio_type == GPIO_TYPE_V2) {
|
||||
gc->reg_writel = gpio_writel_v2;
|
||||
gc->reg_readl = gpio_readl_v2;
|
||||
}
|
||||
gc->reg_base = bank->reg_base;
|
||||
gc->private = bank;
|
||||
gc->chip_types[0].regs.mask = bank->gpio_regs->int_mask;
|
||||
gc->chip_types[0].regs.ack = bank->gpio_regs->port_eoi;
|
||||
gc->chip_types[0].chip.irq_ack = irq_gc_ack_set_bit;
|
||||
gc->chip_types[0].chip.irq_mask = irq_gc_mask_set_bit;
|
||||
gc->chip_types[0].chip.irq_unmask = irq_gc_mask_clr_bit;
|
||||
gc->chip_types[0].chip.irq_enable = irq_gc_mask_clr_bit;
|
||||
gc->chip_types[0].chip.irq_disable = irq_gc_mask_set_bit;
|
||||
gc->chip_types[0].chip.irq_set_wake = irq_gc_set_wake;
|
||||
gc->chip_types[0].chip.irq_suspend = rockchip_irq_suspend;
|
||||
gc->chip_types[0].chip.irq_resume = rockchip_irq_resume;
|
||||
gc->chip_types[0].chip.irq_set_type = rockchip_irq_set_type;
|
||||
gc->wake_enabled = IRQ_MSK(bank->nr_pins);
|
||||
|
||||
/*
|
||||
* Linux assumes that all interrupts start out disabled/masked.
|
||||
* Our driver only uses the concept of masked and always keeps
|
||||
* things enabled, so for us that's all masked and all enabled.
|
||||
*/
|
||||
rockchip_gpio_writel(bank, 0xffffffff, bank->gpio_regs->int_mask);
|
||||
rockchip_gpio_writel(bank, 0xffffffff, bank->gpio_regs->int_en);
|
||||
gc->mask_cache = 0xffffffff;
|
||||
|
||||
irq_set_chained_handler_and_data(bank->irq,
|
||||
rockchip_irq_demux, bank);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int rockchip_gpiolib_register(struct rockchip_pin_bank *bank)
|
||||
{
|
||||
struct gpio_chip *gc;
|
||||
int ret;
|
||||
|
||||
bank->gpio_chip = rockchip_gpiolib_chip;
|
||||
|
||||
gc = &bank->gpio_chip;
|
||||
gc->base = bank->pin_base;
|
||||
gc->ngpio = bank->nr_pins;
|
||||
gc->label = bank->name;
|
||||
gc->parent = bank->dev;
|
||||
#ifdef CONFIG_OF_GPIO
|
||||
gc->of_node = of_node_get(bank->of_node);
|
||||
#endif
|
||||
|
||||
ret = gpiochip_add_data(gc, bank);
|
||||
if (ret) {
|
||||
dev_err(bank->dev, "failed to add gpiochip %s, %d\n", gc->label, ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
/*
|
||||
* For DeviceTree-supported systems, the gpio core checks the
|
||||
* pinctrl's device node for the "gpio-ranges" property.
|
||||
* If it is present, it takes care of adding the pin ranges
|
||||
* for the driver. In this case the driver can skip ahead.
|
||||
*
|
||||
* In order to remain compatible with older, existing DeviceTree
|
||||
* files which don't set the "gpio-ranges" property or systems that
|
||||
* utilize ACPI the driver has to call gpiochip_add_pin_range().
|
||||
*/
|
||||
if (!of_property_read_bool(bank->of_node, "gpio-ranges")) {
|
||||
struct device_node *pctlnp = of_get_parent(bank->of_node);
|
||||
struct pinctrl_dev *pctldev = NULL;
|
||||
|
||||
if (!pctlnp)
|
||||
return -ENODATA;
|
||||
|
||||
pctldev = of_pinctrl_get(pctlnp);
|
||||
if (!pctldev)
|
||||
return -ENODEV;
|
||||
|
||||
ret = gpiochip_add_pin_range(gc, dev_name(pctldev->dev), 0, gc->base, gc->ngpio);
|
||||
if (ret) {
|
||||
dev_err(bank->dev, "Failed to add pin range\n");
|
||||
goto fail;
|
||||
}
|
||||
}
|
||||
|
||||
ret = rockchip_interrupts_register(bank);
|
||||
if (ret) {
|
||||
dev_err(bank->dev, "failed to register interrupt, %d\n", ret);
|
||||
goto fail;
|
||||
}
|
||||
|
||||
return 0;
|
||||
|
||||
fail:
|
||||
gpiochip_remove(&bank->gpio_chip);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int rockchip_get_bank_data(struct rockchip_pin_bank *bank)
|
||||
{
|
||||
struct resource res;
|
||||
int id = 0;
|
||||
|
||||
if (of_address_to_resource(bank->of_node, 0, &res))
|
||||
return -ENOENT;
|
||||
|
||||
bank->reg_base = devm_ioremap_resource(bank->dev, &res);
|
||||
if (IS_ERR(bank->reg_base))
|
||||
return PTR_ERR(bank->reg_base);
|
||||
|
||||
bank->irq = irq_of_parse_and_map(bank->of_node, 0);
|
||||
if (!bank->irq)
|
||||
return -EINVAL;
|
||||
|
||||
bank->clk = of_clk_get(bank->of_node, 0);
|
||||
if (IS_ERR(bank->clk))
|
||||
return PTR_ERR(bank->clk);
|
||||
|
||||
clk_prepare_enable(bank->clk);
|
||||
id = readl(bank->reg_base + gpio_regs_v2.version_id);
|
||||
|
||||
/* If not gpio v2, that is default to v1. */
|
||||
if (id == GPIO_TYPE_V2) {
|
||||
bank->gpio_regs = &gpio_regs_v2;
|
||||
bank->gpio_type = GPIO_TYPE_V2;
|
||||
bank->db_clk = of_clk_get(bank->of_node, 1);
|
||||
if (IS_ERR(bank->db_clk)) {
|
||||
dev_err(bank->dev, "cannot find debounce clk\n");
|
||||
bank->db_clk = NULL;
|
||||
return -EINVAL;
|
||||
}
|
||||
} else {
|
||||
bank->gpio_regs = &gpio_regs_v1;
|
||||
bank->gpio_type = GPIO_TYPE_V1;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int rockchip_gpio_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct device *dev = &pdev->dev;
|
||||
struct device_node *np = pdev->dev.of_node;
|
||||
struct rockchip_pin_bank *bank;
|
||||
static int gpio;
|
||||
int ret;
|
||||
int id;
|
||||
|
||||
bank = devm_kzalloc(dev, sizeof(*bank), GFP_KERNEL);
|
||||
if (!bank)
|
||||
return -ENOMEM;
|
||||
|
||||
if (!np)
|
||||
return -ENODEV;
|
||||
|
||||
id = of_alias_get_id(np, "gpio");
|
||||
if (id < 0)
|
||||
id = gpio++;
|
||||
|
||||
bank->name = devm_kasprintf(dev, GFP_KERNEL, "%pOF", np);
|
||||
bank->pin_base = id * GPIO_BANK_PIN_NUM;
|
||||
bank->nr_pins = GPIO_BANK_PIN_NUM;
|
||||
bank->dev = dev;
|
||||
bank->of_node = dev->of_node;
|
||||
|
||||
raw_spin_lock_init(&bank->slock);
|
||||
|
||||
ret = rockchip_get_bank_data(bank);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
ret = rockchip_gpiolib_register(bank);
|
||||
if (ret)
|
||||
goto err_clk;
|
||||
|
||||
platform_set_drvdata(pdev, bank);
|
||||
dev_info(dev, "probed %s (%s)\n", bank->name, dev_name(dev));
|
||||
|
||||
return 0;
|
||||
err_clk:
|
||||
clk_disable_unprepare(bank->clk);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int rockchip_gpio_remove(struct platform_device *pdev)
|
||||
{
|
||||
struct rockchip_pin_bank *bank = platform_get_drvdata(pdev);
|
||||
|
||||
clk_disable_unprepare(bank->clk);
|
||||
gpiochip_remove(&bank->gpio_chip);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct of_device_id rockchip_gpio_match[] = {
|
||||
{ .compatible = "rockchip,gpio-bank", },
|
||||
{ .compatible = "rockchip,rk3188-gpio-bank0" },
|
||||
{ },
|
||||
};
|
||||
|
||||
static struct platform_driver rockchip_gpio_driver = {
|
||||
.probe = rockchip_gpio_probe,
|
||||
.remove = rockchip_gpio_remove,
|
||||
.driver = {
|
||||
.name = "rockchip-gpio",
|
||||
.of_match_table = rockchip_gpio_match,
|
||||
},
|
||||
};
|
||||
|
||||
static int __init rockchip_gpio_init(void)
|
||||
{
|
||||
return platform_driver_register(&rockchip_gpio_driver);
|
||||
}
|
||||
postcore_initcall(rockchip_gpio_init);
|
||||
|
||||
static void __exit rockchip_gpio_exit(void)
|
||||
{
|
||||
platform_driver_unregister(&rockchip_gpio_driver);
|
||||
}
|
||||
module_exit(rockchip_gpio_exit);
|
||||
|
||||
MODULE_DESCRIPTION("Rockchip gpio driver");
|
||||
MODULE_ALIAS("platform:rockchip-gpio");
|
||||
MODULE_LICENSE("GPL v2");
|
||||
MODULE_DEVICE_TABLE(of, rockchip_gpio_match);
|
||||
Reference in New Issue
Block a user