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clk: rockchip: rk3568: export PCLK_CORE_PVTM clock id

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mark pclk_core_pre as critical.

Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Change-Id: I7da6a93dc1352acb2b336006bd1e30c49b8d6074
This commit is contained in:
Elaine Zhang
2020-09-25 10:53:44 +08:00
committed by Tao Huang
parent 9190b05f4a
commit b3912fea8a
2 changed files with 5 additions and 1 deletions
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3
drivers/clk/rockchip/clk-rk3568.c
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@@ -531,6 +531,8 @@ static struct rockchip_clk_branch rk3568_clk_branches[] __initdata = {
RK3568_CLKGATE_CON(1), 11, GFLAGS),
GATE(CLK_CORE_PVTPLL, "clk_core_pvtpll", "armclk", 0,
RK3568_CLKGATE_CON(1), 12, GFLAGS),
GATE(PCLK_CORE_PVTM, "pclk_core_pvtm", "pclk_core_pre", 0,
RK3568_CLKGATE_CON(1), 9, GFLAGS),
/* PD_GPU */
COMPOSITE(CLK_GPU_SRC, "clk_gpu_src", mpll_gpll_cpll_npll_p, 0,
@@ -1584,6 +1586,7 @@ static struct rockchip_clk_branch rk3568_clk_pmu_branches[] __initdata = {
static const char *const rk3568_cru_critical_clocks[] __initconst = {
"armclk",
"pclk_core_pre",
"aclk_bus",
"pclk_bus",
"aclk_top_high",

3
include/dt-bindings/clock/rk3568-cru.h
View File

@@ -461,8 +461,9 @@
#define SCLK_EMMC_DRV 400
#define SCLK_EMMC_SAMPLE 401
#define PCLK_EDPPHY_GRF 402
#define PCLK_CORE_PVTM 403
#define CLK_NR_CLKS (PCLK_EDPPHY_GRF + 1)
#define CLK_NR_CLKS (PCLK_CORE_PVTM + 1)
/* pmu soft-reset indices */
/* pmucru_softrst_con0 */