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clk: rockchip: rk3568: export PCLK_EDPPHY_GRF clock id

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Change-Id: Ic16fbe5ab6831d7797d417bfce75d9a3c3964fe4
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
This commit is contained in:
Elaine Zhang
2020-09-24 16:08:18 +08:00
committed by Tao Huang
parent 891307ee1d
commit 9190b05f4a
2 changed files with 4 additions and 1 deletions
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2
drivers/clk/rockchip/clk-rk3568.c
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@@ -1463,6 +1463,8 @@ static struct rockchip_clk_branch rk3568_clk_branches[] __initdata = {
RK3568_CLKGATE_CON(34), 12, GFLAGS),
GATE(PCLK_OTPPHY, "pclk_otpphy", "pclk_top", 0,
RK3568_CLKGATE_CON(34), 13, GFLAGS),
GATE(PCLK_EDPPHY_GRF, "pclk_edpphy_grf", "pclk_top", 0,
RK3568_CLKGATE_CON(34), 14, GFLAGS),
};
static struct rockchip_clk_branch rk3568_clk_pmu_branches[] __initdata = {

3
include/dt-bindings/clock/rk3568-cru.h
View File

@@ -460,8 +460,9 @@
#define SCLK_SDMMC2_SAMPLE 399
#define SCLK_EMMC_DRV 400
#define SCLK_EMMC_SAMPLE 401
#define PCLK_EDPPHY_GRF 402
#define CLK_NR_CLKS (SCLK_EMMC_SAMPLE + 1)
#define CLK_NR_CLKS (PCLK_EDPPHY_GRF + 1)
/* pmu soft-reset indices */
/* pmucru_softrst_con0 */