shinys000114/linux
1
0
Fork 0
mirror of https://github.com/hardkernel/linux.git synced 2026-06-07 03:15:31 +09:00
Code Issues Packages Projects Releases Wiki Activity

phy: rockchip: naneng-combphy: Add config for rk3588 pcie

Browse Source 
This patch aims to configure pcie for better compatibility.
1.PLL LPF C1 85pf R1 1.25kohm
2.ck100m_pcie from PLL

Change-Id: I5115cf6ce7341c0891f13639f2c59db86ae9014b
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
This commit is contained in:
Jon Lin
2021-12-08 14:36:47 +08:00
committed by Tao Huang
parent b48a277602
commit 8263003c28
1 changed files with 17 additions and 1 deletions
Download Patch File Download Diff File Expand all files Collapse all files

18
drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
View File

@@ -748,7 +748,23 @@ static int rk3588_combphy_cfg(struct rockchip_combphy_priv *priv)
break;
case 100000000:
param_write(priv->phy_grf, &cfg->pipe_clk_100m, true);
if (priv->mode == PHY_TYPE_SATA) {
if (priv->mode == PHY_TYPE_PCIE) {
/* PLL KVCO tuning fine */
val = readl(priv->mmio + (0x20 << 2));
val &= ~GENMASK(4, 2);
val |= 0x4 << 2;
writel(val, priv->mmio + (0x20 << 2));
/* Set up rx_trim: PLL LPF C1 85pf R1 1.25kohm */
val = 0x4c;
writel(val, priv->mmio + (0x1b << 2));
/* Set up su_trim: */
val = 0xf0;
writel(val, priv->mmio + (0xa << 2));
val = 0x4;
writel(val, priv->mmio + (0xb << 2));
} else if (priv->mode == PHY_TYPE_SATA) {
/* downward spread spectrum +500ppm */
val = readl(priv->mmio + (0x1f << 2));
val &= ~GENMASK(7, 4);