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clk: rockchip: rk3576: add PCLK_DDR_MON_CH for ddr monitor

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Change-Id: I2239f6d96d144f7a314a7df2fd2fe60477464233
Signed-off-by: Zhihuan He <huan.he@rock-chips.com>
This commit is contained in:
Zhihuan He
2024-10-30 17:27:01 +08:00
committed by Tao Huang
parent dfb8a71ba3
commit 827bf4adc0
1 changed files with 3 additions and 1 deletions
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4
drivers/clk/rockchip/clk-rk3576.c
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@@ -878,8 +878,10 @@ static struct rockchip_clk_branch rk3576_clk_branches[] __initdata = {
COMPOSITE(PCLK_DDR_ROOT, "pclk_ddr_root", gpll_cpll_24m_p, CLK_IS_CRITICAL,
RK3576_CLKSEL_CON(76), 5, 2, MFLAGS, 0, 5, DFLAGS,
RK3576_CLKGATE_CON(21), 0, GFLAGS),
GATE(PCLK_DDR_MON_CH0, "pclk_ddr_mon_ch0", "pclk_ddr_root", CLK_IGNORE_UNUSED,
GATE(PCLK_DDR_MON_CH0, "pclk_ddr_mon_ch0", "pclk_ddr_root", 0,
RK3576_CLKGATE_CON(21), 1, GFLAGS),
GATE(PCLK_DDR_MON_CH1, "pclk_ddr_mon_ch1", "pclk_ddr_root", 0,
RK3576_CLKGATE_CON(21), 14, GFLAGS),
COMPOSITE(HCLK_DDR_ROOT, "hclk_ddr_root", gpll_cpll_p, CLK_IGNORE_UNUSED,
RK3576_CLKSEL_CON(77), 5, 1, MFLAGS, 0, 5, DFLAGS,
RK3576_CLKGATE_CON(22), 11, GFLAGS),