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phy: rockchip: naneng-combphy: fix U3 RX long cable test failed for RK3528

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1.Set slow slew rate control for PI
2.Set CDR phase path with 2x gain

Signed-off-by: Jianwei Zheng <jianwei.zheng@rock-chips.com>
Change-Id: I2d0811b0be7b1d4764ecd738d069b06e4da5eaa2
This commit is contained in:
Jianwei Zheng
2023-08-10 17:20:39 +08:00
committed by Tao Huang
parent fe72550de7
commit 863c95ebe8
1 changed files with 6 additions and 0 deletions
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6
drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
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@@ -458,6 +458,12 @@ static int rk3528_combphy_cfg(struct rockchip_combphy_priv *priv)
/* Enable adaptive CTLE for USB3.0 Rx */
rockchip_combphy_updatel(priv, GENMASK(17, 17), BIT(17), 0x200);
/* Set slow slew rate control for PI */
rockchip_combphy_updatel(priv, GENMASK(2, 0), 0x07, 0x204);
/* Set CDR phase path with 2x gain */
rockchip_combphy_updatel(priv, GENMASK(5, 5), BIT(5), 0x204);
/* Set Rx squelch input filler bandwidth */
rockchip_combphy_updatel(priv, GENMASK(2, 0), 0x06, 0x20c);