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arm64: dts: rockchip: rk3588: add pcie controller support
The rk3588 supports 5 controllers: - 1 pcie3x4; - 1 pcie3x2; - 3 pcie2x1(2 of them also available in rk3588s); Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Change-Id: Icae3a5539ace233141ff7f89600d17758be7fa5c
This commit is contained in:
Kever Yang
@@ -37,6 +37,11 @@
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};
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};
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pcie30_phy_grf: syscon@fd5b8000 {
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compatible = "rockchip,pcie30-phy-grf", "syscon";
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reg = <0x0 0xfd5b8000 0x0 0x10000>;
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};
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pipe_phy1_grf: syscon@fd5c0000 {
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compatible = "rockchip,pipe-phy-grf", "syscon";
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reg = <0x0 0xfd5c0000 0x0 0x100>;
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@@ -178,6 +183,159 @@
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status = "disabled";
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};
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pcie3x4: pcie@fe150000 {
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compatible = "rockchip,rk3588-pcie", "snps,dw-pcie";
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#address-cells = <3>;
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#size-cells = <2>;
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bus-range = <0x00 0x0f>;
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clocks = <&cru ACLK_PCIE_4L_MSTR>, <&cru ACLK_PCIE_4L_SLV>,
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<&cru ACLK_PCIE_4L_DBI>, <&cru PCLK_PCIE_4L>,
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<&cru CLK_PCIE_AUX0>;
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clock-names = "aclk_mst", "aclk_slv",
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"aclk_dbi", "pclk", "aux";
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device_type = "pci";
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interrupts = <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "sys", "pmc", "msg", "legacy", "err";
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#interrupt-cells = <1>;
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interrupt-map-mask = <0 0 0 7>;
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interrupt-map = <0 0 0 1 &pcie3x4_intc 0>,
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<0 0 0 2 &pcie3x4_intc 1>,
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<0 0 0 3 &pcie3x4_intc 2>,
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<0 0 0 4 &pcie3x4_intc 3>;
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linux,pci-domain = <0>;
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num-ib-windows = <16>;
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num-ob-windows = <16>;
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max-link-speed = <3>;
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msi-map = <0x0000 &its 0x0000 0x1000>;
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num-lanes = <4>;
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phys = <&pcie30phy>;
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phy-names = "pcie-phy";
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power-domains = <&power RK3588_PD_PHP>;
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ranges = <0x00000800 0x0 0x80000000 0x9 0x00000000 0x0 0x800000
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0x81000000 0x0 0x80800000 0x9 0x00800000 0x0 0x100000
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0x83000000 0x0 0x80900000 0x9 0x00900000 0x0 0x3f700000>;
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reg = <0xa 0x40000000 0x0 0x400000>,
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<0x0 0xfe150000 0x0 0x10000>;
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reg-names = "pcie-dbi", "pcie-apb";
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resets = <&cru SRST_PCIE0_POWER_UP>;
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reset-names = "pipe";
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status = "disabled";
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pcie3x4_intc: legacy-interrupt-controller {
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interrupt-controller;
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#address-cells = <0>;
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#interrupt-cells = <1>;
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interrupt-parent = <&gic>;
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interrupts = <GIC_SPI 260 IRQ_TYPE_EDGE_RISING>;
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};
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};
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pcie3x2: pcie@fe160000 {
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compatible = "rockchip,rk3588-pcie", "snps,dw-pcie";
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#address-cells = <3>;
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#size-cells = <2>;
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bus-range = <0x10 0x1f>;
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clocks = <&cru ACLK_PCIE_2L_MSTR>, <&cru ACLK_PCIE_2L_SLV>,
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<&cru ACLK_PCIE_2L_DBI>, <&cru PCLK_PCIE_2L>,
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<&cru CLK_PCIE_AUX1>;
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clock-names = "aclk_mst", "aclk_slv",
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"aclk_dbi", "pclk", "aux";
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device_type = "pci";
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interrupts = <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "sys", "pmc", "msg", "legacy", "err";
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#interrupt-cells = <1>;
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interrupt-map-mask = <0 0 0 7>;
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interrupt-map = <0 0 0 1 &pcie3x2_intc 0>,
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<0 0 0 2 &pcie3x2_intc 1>,
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<0 0 0 3 &pcie3x2_intc 2>,
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<0 0 0 4 &pcie3x2_intc 3>;
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linux,pci-domain = <1>;
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num-ib-windows = <16>;
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num-ob-windows = <16>;
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max-link-speed = <3>;
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msi-map = <0x1000 &its 0x1000 0x1000>;
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num-lanes = <2>;
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phys = <&pcie30phy>;
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phy-names = "pcie-phy";
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power-domains = <&power RK3588_PD_PHP>;
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ranges = <0x00000800 0x0 0x80000000 0x9 0x40000000 0x0 0x800000
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0x81000000 0x0 0x80800000 0x9 0x40800000 0x0 0x100000
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0x83000000 0x0 0x80900000 0x9 0x40900000 0x0 0x3f700000>;
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reg = <0xa 0x40400000 0x0 0x400000>,
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<0x0 0xfe160000 0x0 0x10000>;
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reg-names = "pcie-dbi", "pcie-apb";
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resets = <&cru SRST_PCIE1_POWER_UP>;
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reset-names = "pipe";
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status = "disabled";
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pcie3x2_intc: legacy-interrupt-controller {
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interrupt-controller;
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#address-cells = <0>;
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#interrupt-cells = <1>;
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interrupt-parent = <&gic>;
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interrupts = <GIC_SPI 255 IRQ_TYPE_EDGE_RISING>;
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};
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};
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pcie2x1l0: pcie@fe170000 {
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compatible = "rockchip,rk3588-pcie", "snps,dw-pcie";
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#address-cells = <3>;
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#size-cells = <2>;
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bus-range = <0x20 0x2f>;
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clocks = <&cru ACLK_PCIE_1L0_MSTR>, <&cru ACLK_PCIE_1L0_SLV>,
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<&cru ACLK_PCIE_1L0_DBI>, <&cru PCLK_PCIE_1L0>,
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<&cru CLK_PCIE_AUX2>;
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clock-names = "aclk_mst", "aclk_slv",
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"aclk_dbi", "pclk", "aux";
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device_type = "pci";
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interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "sys", "pmc", "msg", "legacy", "err";
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#interrupt-cells = <1>;
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interrupt-map-mask = <0 0 0 7>;
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interrupt-map = <0 0 0 1 &pcie2x1l0_intc 0>,
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<0 0 0 2 &pcie2x1l0_intc 1>,
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<0 0 0 3 &pcie2x1l0_intc 2>,
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<0 0 0 4 &pcie2x1l0_intc 3>;
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linux,pci-domain = <2>;
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num-ib-windows = <8>;
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num-ob-windows = <8>;
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max-link-speed = <2>;
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msi-map = <0x2000 &its 0x2000 0x1000>;
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num-lanes = <1>;
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phys = <&combphy1_ps PHY_TYPE_PCIE>;
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phy-names = "pcie-phy";
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power-domains = <&power RK3588_PD_PHP>;
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ranges = <0x00000800 0x0 0x80000000 0x9 0x80000000 0x0 0x800000
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0x81000000 0x0 0x80800000 0x9 0x80800000 0x0 0x100000
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0x83000000 0x0 0x80900000 0x9 0x80900000 0x0 0x3f700000>;
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reg = <0xa 0x40800000 0x0 0x400000>,
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<0x0 0xfe170000 0x0 0x10000>;
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reg-names = "pcie-dbi", "pcie-apb";
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resets = <&cru SRST_PCIE2_POWER_UP>;
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reset-names = "pipe";
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status = "disabled";
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pcie2x1l0_intc: legacy-interrupt-controller {
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interrupt-controller;
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#address-cells = <0>;
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#interrupt-cells = <1>;
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interrupt-parent = <&gic>;
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interrupts = <GIC_SPI 240 IRQ_TYPE_EDGE_RISING>;
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};
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};
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gmac0: ethernet@fe1b0000 {
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compatible = "rockchip,rk3588-gmac", "snps,dwmac-4.20a";
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reg = <0x0 0xfe1b0000 0x0 0x10000>;
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@@ -284,4 +442,17 @@
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rockchip,pipe-phy-grf = <&pipe_phy1_grf>;
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status = "disabled";
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};
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pcie30phy: phy@fee80000 {
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compatible = "rockchip,rk3588-pcie3-phy";
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reg = <0x0 0xfee80000 0x0 0x20000>;
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#phy-cells = <0>;
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clocks = <&cru PCLK_PCIE_COMBO_PIPE_PHY>;
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clock-names = "pclk";
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resets = <&cru SRST_PCIE30_PHY>;
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reset-names = "phy";
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rockchip,phy-grf = <&pcie30_phy_grf>;
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status = "disabled";
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};
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};
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