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drm/rockchip: vop2: get correct dclk source when fixup dclk rate

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For rk3576 and rk3588, vop dclk can be from pll or hdmi phy[except hdmi
2.1(dclk bigger than 597M), the HDMI work at FRL mode], when dclk is
from pll, dclk_parent is equal to dclk, we need clk_round_rate() for
dclk_parent to check whether can support this mode.

1. GPLL/CPLL/VPLL
       dclk_parent
           dclk

2. xin24m
       clk_hdmiphy_pixel0
           dclk

Change-Id: Ie5b9a7a5056a6f997ade95ab6af9b6d7ddc10f3b
Signed-off-by: Zhang Yubing <yubing.zhang@rock-chips.com>
This commit is contained in:
Zhang Yubing
2024-05-28 09:32:38 +08:00
committed by Tao Huang
parent 915826d691
commit 89b7bdea30
1 changed files with 4 additions and 2 deletions
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6
drivers/gpu/drm/rockchip/rockchip_drm_vop2.c
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@@ -7896,8 +7896,10 @@ static bool vop2_crtc_mode_fixup(struct drm_crtc *crtc,
drm_connector_list_iter_end(&conn_iter);
if (adj_mode->crtc_clock <= VOP2_MAX_DCLK_RATE) {
adj_mode->crtc_clock = rockchip_drm_dclk_round_rate(vop2->version, vp->dclk,
adj_mode->crtc_clock * 1000);
adj_mode->crtc_clock =
rockchip_drm_dclk_round_rate(vop2->version,
vp->dclk_parent ? vp->dclk_parent : vp->dclk,
adj_mode->crtc_clock * 1000);
adj_mode->crtc_clock = DIV_ROUND_UP(adj_mode->crtc_clock, 1000);
}
return true;