Zhang Yubing 89b7bdea30 drm/rockchip: vop2: get correct dclk source when fixup dclk rate
For rk3576 and rk3588, vop dclk can be from pll or hdmi phy[except hdmi
2.1(dclk bigger than 597M), the HDMI work at FRL mode], when dclk is
from pll, dclk_parent is equal to dclk, we need clk_round_rate() for
dclk_parent to check whether can support this mode.

1. GPLL/CPLL/VPLL
       dclk_parent
           dclk

2. xin24m
       clk_hdmiphy_pixel0
           dclk

Change-Id: Ie5b9a7a5056a6f997ade95ab6af9b6d7ddc10f3b
Signed-off-by: Zhang Yubing <yubing.zhang@rock-chips.com>
2024-05-30 20:42:47 +08:00
2024-05-08 11:14:32 +08:00
2024-05-08 11:14:32 +08:00
2024-05-08 11:14:32 +08:00
2024-05-08 11:14:32 +08:00
2024-05-08 11:14:32 +08:00
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2024-05-08 11:14:32 +08:00
2022-09-28 09:02:20 +02:00
2024-01-25 15:27:52 -08:00

Linux kernel
============

There are several guides for kernel developers and users. These guides can
be rendered in a number of formats, like HTML and PDF. Please read
Documentation/admin-guide/README.rst first.

In order to build the documentation, use ``make htmldocs`` or
``make pdfdocs``.  The formatted documentation can also be read online at:

    https://www.kernel.org/doc/html/latest/

There are various text files in the Documentation/ subdirectory,
several of them using the Restructured Text markup notation.

Please read the Documentation/process/changes.rst file, as it contains the
requirements for building and running the kernel, and information about
the problems which may result by upgrading your kernel.
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