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ASoC: rockchip: sai: Handle clk enable in prepare stage
Currently, the BCLK/FSYNC enable is addressed in hw_params stage, because the real clk is measured by samplerate. so, it is quite a good solution. But, on the system PM situation, it is failed to recovery BCLK/LRCK after resume. the root cause is that never do 'hw_params' after resume. which is similar to XRUN issue. So, let's move it to prepare stage which any path must do before trigger-start. Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com> Change-Id: I9025a98259a4e9bd9f09ec3d23584f753552031d
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@@ -506,6 +506,17 @@ static int rockchip_sai_hw_params(struct snd_pcm_substream *substream,
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regmap_update_bits(sai->regmap, SAI_CKR, SAI_CKR_MDIV_MASK,
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SAI_CKR_MDIV(div_bclk));
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}
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return 0;
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}
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static int rockchip_sai_prepare(struct snd_pcm_substream *substream,
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struct snd_soc_dai *dai)
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{
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struct rk_sai_dev *sai = snd_soc_dai_get_drvdata(dai);
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if (sai->is_master_mode) {
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/*
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* Should wait for one BCLK ready after DIV and then ungate
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* output clk to achieve the clean clk.
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@@ -628,6 +639,7 @@ static const struct snd_soc_dai_ops rockchip_sai_dai_ops = {
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.hw_params = rockchip_sai_hw_params,
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.set_sysclk = rockchip_sai_set_sysclk,
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.set_fmt = rockchip_sai_set_fmt,
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.prepare = rockchip_sai_prepare,
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.trigger = rockchip_sai_trigger,
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.set_tdm_slot = rockchip_sai_set_tdm_slot,
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};
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