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video: disable vd1 post and pre as default

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PD#156734

Change-Id: I43b372d55e4997999fe7c99ea9d0ab4f7b8a5e57
Signed-off-by: Brian Zhu <brian.zhu@amlogic.com>
This commit is contained in:
Brian Zhu
2018-02-02 00:28:21 +08:00
committed by Yixun Lan
parent 082e51e3f8
commit 8a6c1e2780
2 changed files with 6 additions and 8 deletions
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6
drivers/amlogic/media/enhancement/amvecm/bitdepth.c
View File

@@ -380,11 +380,11 @@ void vpp_set_12bit_datapath_g12a(void)
vpp_set_vd1_mux4(0);
vpp_set_vd1_mux2(0);
vpp_set_vd1_mux5(0);
vpp_set_vd1_preblend_mux(1);
vpp_set_vd1_postblend_mux(1);
vpp_set_vd1_preblend_mux(0);
vpp_set_vd1_postblend_mux(0);
vpp_set_vd1_postblend_en(1);
vpp_set_vd2_preblend_mux(0);
vpp_set_vd2_postblend_mux(2);
vpp_set_vd2_postblend_mux(0);
vpp_set_vd2_postblend_en(0);
vpp_set_vd2_ext_mod(0);
vpp_set_vd2_bypass_dolby(1);

8
drivers/amlogic/media/video_sink/video.c
View File

@@ -5560,11 +5560,11 @@ SET_FILTER:
set_value =
((1 << 20) |
(1 << 16) | /* post bld premult*/
(1 << 8)); /* post src */
(2 << 8)); /* post src */
else if (vpp_misc_set & VPP_VD2_PREBLEND)
set_value =
((1 << 4) | /* pre bld premult*/
(1 << 0)); /* pre bld src 1 */
(2 << 0)); /* pre bld src 1 */
VSYNC_WR_MPEG_REG(
VD2_BLEND_SRC_CTRL + cur_dev->vpp_off,
set_value);
@@ -5575,9 +5575,7 @@ SET_FILTER:
if ((vpp_misc_set & VPP_VD2_PREBLEND)
&& (vpp_misc_set & VPP_VD1_PREBLEND))
set_value |= VPP_PREBLEND_EN;
if ((vpp_misc_set & VPP_VD2_POSTBLEND)
|| (vpp_misc_set & VPP_VD1_POSTBLEND))
set_value |= VPP_POSTBLEND_EN;
set_value |= VPP_POSTBLEND_EN;
VSYNC_WR_MPEG_REG(
VPP_MISC + cur_dev->vpp_off,
set_value);