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ARM: dts: rockchip: rk3506g-demo-display-control: fix noise dues to mclk and coeffs without matched

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The requirements of rk3506 codec are mainly divided into three
sampling rate groups: 48/44.1/32kHz.

And, the rk3506 codec has internal frequency division, the driver
limits these three mclk inputs:
 #define MCLK_REFERENCE_8000 32768000
 #define MCLK_REFERENCE_11025 45158400
 #define MCLK_REFERENCE_12000 49152000

Therefore, it is necessary to add the "rockchip,mclk-no-set" property
to the SAI4 to avoid switching the mclk frequency in the function of
rockchip_sai_set_sysclk() after the codec configures mclk, causing
the codec filter to work abnormally.

Change-Id: Ic6cd0688287eb4c92c3b27bba4f60c46610c9006
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
This commit is contained in:
Xing Zheng
2025-01-09 17:21:10 +08:00
committed by Tao Huang
parent c48bb00056
commit 8a89e948a2
1 changed files with 2 additions and 0 deletions
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2
arch/arm/boot/dts/rk3506g-demo-display-control.dts
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@@ -591,6 +591,7 @@
&sai1 {
status = "okay";
rockchip,mclk-no-set;
pinctrl-names = "default";
pinctrl-0 = <&rm_io9_sai1_sclk
&rm_io10_sai1_lrck
@@ -600,6 +601,7 @@
&sai4 {
status = "okay";
rockchip,mclk-no-set;
};
&saradc {