mirror of
https://github.com/hardkernel/linux.git
synced 2026-06-05 10:31:46 +09:00
Merge commit 'f9324b0e31d0dbe11cc2faf6d360e838aa8b14c4'
* commit 'f9324b0e31d0dbe11cc2faf6d360e838aa8b14c4': ARM: configs: rv1126b_defconfig: Disable CONFIG_ROCKCHIP_PVTM ARM: configs: add rv1126b_linux_defconfig to support RV1126B SoC with Linux OS media: rockchip: vpss: set ROCKIT_BUF_NUM_MAX to 20 media: i2c: rk628: fix read timing err soc: rockchip: opp_select: Fix memleak in rockchip_opp_set_config() media: rockchip: vicap fixes yuv input order error of dvp for rk3576 media: rockchip: fec: Fix incorrect buffer size configuration mm: defer init highmem page when CONFIG_ROCKCHIP_THUNDER_BOOT_DEFER_FREE_MEMBLOCK=y init: use pageblock to free highmem instead of page when CONFIG_ROCKCHIP_THUNDER_BOOT_DEFER_FREE_MEMBLOCK=y media: rockchip: vpss: fix RKVPSS_VPSS_ONLINE value error in offline mode Change-Id: I655c70a12ebc79d0c02ba04b2c20c84e1b782df7
This commit is contained in:
Tao Huang
@@ -17,7 +17,6 @@ CONFIG_NLS_CODEPAGE_936=y
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# CONFIG_PM_DEVFREQ is not set
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# CONFIG_PRINTK_TIME is not set
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# CONFIG_PWM is not set
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# CONFIG_ROCKCHIP_PVTM is not set
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# CONFIG_RTC_CLASS is not set
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# CONFIG_SOUND is not set
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CONFIG_SPI=y
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@@ -175,7 +175,6 @@ CONFIG_CPU_RV1126B=y
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CONFIG_ROCKCHIP_AMP=y
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CONFIG_ROCKCHIP_CPUINFO=y
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CONFIG_ROCKCHIP_PM_DOMAINS=y
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CONFIG_ROCKCHIP_PVTM=y
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CONFIG_ROCKCHIP_SYSTEM_MONITOR=y
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CONFIG_FIQ_DEBUGGER=y
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CONFIG_FIQ_DEBUGGER_NO_SLEEP=y
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343
arch/arm/configs/rv1126b_linux_defconfig
Normal file
343
arch/arm/configs/rv1126b_linux_defconfig
Normal file
@@ -0,0 +1,343 @@
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# CONFIG_LOCALVERSION_AUTO is not set
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CONFIG_KERNEL_XZ=y
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CONFIG_DEFAULT_HOSTNAME="localhost"
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CONFIG_SYSVIPC=y
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CONFIG_NO_HZ_IDLE=y
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CONFIG_HIGH_RES_TIMERS=y
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CONFIG_LOG_BUF_SHIFT=14
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CONFIG_CC_OPTIMIZE_FOR_SIZE=y
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CONFIG_LD_DEAD_CODE_DATA_ELIMINATION=y
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# CONFIG_BUG is not set
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# CONFIG_BASE_FULL is not set
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# CONFIG_IO_URING is not set
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CONFIG_EMBEDDED=y
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CONFIG_ARCH_ROCKCHIP=y
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# CONFIG_HARDEN_BRANCH_PREDICTOR is not set
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# CONFIG_HARDEN_BRANCH_HISTORY is not set
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# CONFIG_VDSO is not set
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# CONFIG_CACHE_L2X0 is not set
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# CONFIG_ARM_ERRATA_643719 is not set
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CONFIG_SMP=y
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CONFIG_SCHED_MC=y
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CONFIG_VMSPLIT_3G_OPT=y
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CONFIG_HOTPLUG_CPU=y
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CONFIG_ARM_PSCI=y
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CONFIG_THUMB2_KERNEL=y
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CONFIG_HIGHMEM=y
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# CONFIG_CPU_SW_DOMAIN_PAN is not set
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CONFIG_ARCH_FORCE_MAX_ORDER=9
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CONFIG_UACCESS_WITH_MEMCPY=y
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# CONFIG_STACKPROTECTOR_PER_TASK is not set
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CONFIG_CMDLINE="user_debug=31"
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CONFIG_CMDLINE_EXTEND=y
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CONFIG_CPU_FREQ=y
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CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y
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CONFIG_CPU_FREQ_GOV_USERSPACE=y
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CONFIG_CPUFREQ_DT=y
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CONFIG_ARM_ROCKCHIP_CPUFREQ=y
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CONFIG_CPU_IDLE=y
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CONFIG_ARM_CPUIDLE=y
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CONFIG_ARM_PSCI_CPUIDLE=y
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# CONFIG_ARM_PSCI_CPUIDLE_DOMAIN is not set
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CONFIG_VFP=y
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CONFIG_NEON=y
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# CONFIG_SUSPEND is not set
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CONFIG_JUMP_LABEL=y
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# CONFIG_SECCOMP is not set
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# CONFIG_STACKPROTECTOR_STRONG is not set
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# CONFIG_STRICT_KERNEL_RWX is not set
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CONFIG_MODULES=y
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CONFIG_MODULE_UNLOAD=y
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CONFIG_PARTITION_ADVANCED=y
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CONFIG_CMDLINE_PARTITION=y
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# CONFIG_MQ_IOSCHED_KYBER is not set
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CONFIG_IOSCHED_BFQ=y
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# CONFIG_SWAP is not set
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CONFIG_KSM=y
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CONFIG_DEFAULT_MMAP_MIN_ADDR=32768
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CONFIG_CMA=y
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CONFIG_CMA_INACTIVE=y
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# CONFIG_VM_EVENT_COUNTERS is not set
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CONFIG_LRU_GEN=y
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CONFIG_LRU_GEN_ENABLED=y
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CONFIG_NET=y
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CONFIG_PACKET=y
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CONFIG_UNIX=y
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CONFIG_INET=y
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CONFIG_INET_TABLE_PERTURB_ORDER=8
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# CONFIG_INET_DIAG is not set
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# CONFIG_IPV6_SIT is not set
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CONFIG_BT=y
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CONFIG_BT_HCIUART=y
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CONFIG_BT_HCIUART_H4=y
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CONFIG_RFKILL=y
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CONFIG_RFKILL_RK=y
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CONFIG_DEVTMPFS=y
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CONFIG_DEVTMPFS_MOUNT=y
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# CONFIG_ALLOW_DEV_COREDUMP is not set
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CONFIG_ROCKCHIP_SIP=y
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CONFIG_MTD=y
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CONFIG_MTD_CMDLINE_PARTS=y
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# CONFIG_MTD_OF_PARTS is not set
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CONFIG_MTD_BLOCK=y
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CONFIG_MTD_SPI_NAND=y
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CONFIG_MTD_SPI_NOR=y
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CONFIG_MTD_SPI_NOR_MISC=y
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# CONFIG_MTD_SPI_NOR_DEVICE_AUTOSELECT is not set
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CONFIG_MTD_SPI_NOR_GIGADEVICE=y
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CONFIG_MTD_SPI_NOR_MACRONIX=y
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CONFIG_MTD_SPI_NOR_WINBOND=y
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CONFIG_MTD_UBI=y
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CONFIG_MTD_UBI_BLOCK=y
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CONFIG_NETDEVICES=y
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# CONFIG_NET_CORE is not set
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CONFIG_STMMAC_ETH=y
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# CONFIG_DWMAC_GENERIC is not set
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CONFIG_ROCKCHIP_FEPHY=y
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# CONFIG_USB_NET_DRIVERS is not set
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# CONFIG_WLAN_VENDOR_ADMTEK is not set
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# CONFIG_WLAN_VENDOR_ATH is not set
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# CONFIG_WLAN_VENDOR_ATMEL is not set
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# CONFIG_WLAN_VENDOR_BROADCOM is not set
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# CONFIG_WLAN_VENDOR_CISCO is not set
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# CONFIG_WLAN_VENDOR_INTEL is not set
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# CONFIG_WLAN_VENDOR_INTERSIL is not set
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# CONFIG_WLAN_VENDOR_MARVELL is not set
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# CONFIG_WLAN_VENDOR_MEDIATEK is not set
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# CONFIG_WLAN_VENDOR_MICROCHIP is not set
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# CONFIG_WLAN_VENDOR_RALINK is not set
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# CONFIG_WLAN_VENDOR_REALTEK is not set
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# CONFIG_WLAN_VENDOR_RSI is not set
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# CONFIG_WLAN_VENDOR_ST is not set
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# CONFIG_WLAN_VENDOR_TI is not set
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# CONFIG_WLAN_VENDOR_ZYDAS is not set
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# CONFIG_WLAN_VENDOR_QUANTENNA is not set
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CONFIG_WL_ROCKCHIP=y
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# CONFIG_BCMDHD is not set
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CONFIG_INPUT_EVDEV=y
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CONFIG_KEYBOARD_ADC=y
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# CONFIG_KEYBOARD_ATKBD is not set
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# CONFIG_INPUT_MOUSE is not set
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# CONFIG_SERIO is not set
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# CONFIG_VT is not set
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# CONFIG_LEGACY_PTYS is not set
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CONFIG_SERIAL_8250=y
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# CONFIG_SERIAL_8250_DEPRECATED_OPTIONS is not set
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# CONFIG_SERIAL_8250_16550A_VARIANTS is not set
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CONFIG_SERIAL_8250_CONSOLE=y
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CONFIG_SERIAL_8250_NR_UARTS=8
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CONFIG_SERIAL_8250_RUNTIME_UARTS=8
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CONFIG_SERIAL_8250_DW=y
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CONFIG_HW_RANDOM=y
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CONFIG_HW_RANDOM_ROCKCHIP=y
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# CONFIG_RANDOM_TRUST_BOOTLOADER is not set
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CONFIG_I2C_CHARDEV=y
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CONFIG_I2C_MUX=y
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CONFIG_I2C_GPIO=y
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CONFIG_I2C_RK3X=y
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CONFIG_SPI=y
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CONFIG_SPI_ROCKCHIP=y
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CONFIG_SPI_ROCKCHIP_SFC=y
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CONFIG_SPI_SPIDEV=y
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# CONFIG_PTP_1588_CLOCK is not set
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CONFIG_GPIO_SYSFS=y
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CONFIG_POWER_RESET=y
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CONFIG_POWER_RESET_RESTART=y
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CONFIG_SYSCON_REBOOT_MODE=y
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CONFIG_POWER_SUPPLY=y
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# CONFIG_HWMON is not set
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CONFIG_THERMAL=y
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CONFIG_THERMAL_WRITABLE_TRIPS=y
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CONFIG_THERMAL_GOV_USER_SPACE=y
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CONFIG_CPU_THERMAL=y
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CONFIG_DEVFREQ_THERMAL=y
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CONFIG_ROCKCHIP_THERMAL=y
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CONFIG_WATCHDOG=y
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CONFIG_DW_WATCHDOG=y
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CONFIG_MFD_RK808=y
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CONFIG_REGULATOR_FIXED_VOLTAGE=y
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CONFIG_REGULATOR_GPIO=y
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CONFIG_REGULATOR_PWM=y
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CONFIG_REGULATOR_RK801=y
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CONFIG_REGULATOR_RK808=y
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CONFIG_MEDIA_SUPPORT=y
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CONFIG_MEDIA_SUPPORT_FILTER=y
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# CONFIG_MEDIA_SUBDRV_AUTOSELECT is not set
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CONFIG_MEDIA_CAMERA_SUPPORT=y
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CONFIG_MEDIA_PLATFORM_SUPPORT=y
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CONFIG_V4L_PLATFORM_DRIVERS=y
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CONFIG_VIDEO_ROCKCHIP_AIISP=y
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CONFIG_VIDEO_ROCKCHIP_AVSP=y
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CONFIG_VIDEO_ROCKCHIP_CIF=y
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CONFIG_VIDEO_ROCKCHIP_FEC=y
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CONFIG_VIDEO_ROCKCHIP_ISP=y
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CONFIG_VIDEO_ROCKCHIP_VPSS=y
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CONFIG_VIDEO_GC2053=y
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CONFIG_VIDEO_GC8613=y
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CONFIG_VIDEO_IMX415=y
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CONFIG_VIDEO_OS04A10=y
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CONFIG_VIDEO_PS5458=y
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CONFIG_VIDEO_SC200AI=y
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CONFIG_VIDEO_SC3336=y
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CONFIG_VIDEO_SC401AI=y
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CONFIG_VIDEO_SC4336=y
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CONFIG_VIDEO_SC450AI=y
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CONFIG_VIDEO_SC530AI=y
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CONFIG_VIDEO_SC635HAI=y
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CONFIG_VIDEO_SC850SL=y
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CONFIG_VIDEO_TECHPOINT=y
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CONFIG_DRM=y
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CONFIG_DRM_IGNORE_IOTCL_PERMIT=y
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CONFIG_DRM_ROCKCHIP=y
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CONFIG_ROCKCHIP_DRM_DEBUG=y
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CONFIG_ROCKCHIP_VOP=y
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CONFIG_ROCKCHIP_DW_MIPI_DSI=y
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CONFIG_ROCKCHIP_RGB=y
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CONFIG_DRM_PANEL_SIMPLE=y
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CONFIG_DRM_PANEL_SIMPLE_OF_ONLY=y
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CONFIG_BACKLIGHT_CLASS_DEVICE=y
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CONFIG_BACKLIGHT_PWM=y
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CONFIG_ROCKCHIP_MULTI_RGA=y
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CONFIG_ROCKCHIP_RGA_PROC_FS=y
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# CONFIG_ROCKCHIP_RGA_DEBUG_FS is not set
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CONFIG_ROCKCHIP_MPP_OSAL=y
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CONFIG_ROCKCHIP_DVBM=y
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CONFIG_SOUND=y
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CONFIG_SND=y
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# CONFIG_SND_PCM_TIMER is not set
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# CONFIG_SND_SUPPORT_OLD_API is not set
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# CONFIG_SND_DRIVERS is not set
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# CONFIG_SND_ARM is not set
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# CONFIG_SND_SPI is not set
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CONFIG_SND_SOC=y
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CONFIG_SND_SOC_ROCKCHIP=y
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CONFIG_SND_SOC_ROCKCHIP_ASRC=y
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CONFIG_SND_SOC_ROCKCHIP_PDM_V2=y
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CONFIG_SND_SOC_ROCKCHIP_SAI=y
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CONFIG_SND_SOC_ROCKCHIP_MULTICODECS=y
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CONFIG_SND_SOC_DUMMY_CODEC=y
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CONFIG_SND_SOC_RK3506=y
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CONFIG_SND_SOC_RK817=y
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CONFIG_SND_SOC_RK_DSM=y
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CONFIG_SND_SIMPLE_CARD=y
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# CONFIG_HID is not set
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# CONFIG_USB_HID is not set
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CONFIG_USB=y
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CONFIG_USB_XHCI_HCD=y
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CONFIG_USB_EHCI_HCD=y
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CONFIG_USB_EHCI_HCD_PLATFORM=y
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CONFIG_USB_OHCI_HCD=y
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CONFIG_USB_OHCI_HCD_PLATFORM=y
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CONFIG_USB_DWC3=y
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CONFIG_USB_GADGET=y
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CONFIG_USB_GADGET_VBUS_DRAW=500
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CONFIG_USB_CONFIGFS=y
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CONFIG_USB_CONFIGFS_UEVENT=y
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CONFIG_USB_CONFIGFS_F_FS=y
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||||
CONFIG_USB_CONFIGFS_F_UAC1=y
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||||
CONFIG_USB_CONFIGFS_F_UAC2=y
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||||
CONFIG_USB_CONFIGFS_F_HID=y
|
||||
CONFIG_USB_CONFIGFS_F_UVC=y
|
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CONFIG_MMC=y
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||||
# CONFIG_PWRSEQ_EMMC is not set
|
||||
CONFIG_MMC_BLOCK_MINORS=32
|
||||
CONFIG_MMC_QUEUE_DEPTH=1
|
||||
CONFIG_MMC_DW=y
|
||||
CONFIG_MMC_DW_ROCKCHIP=y
|
||||
CONFIG_RTC_CLASS=y
|
||||
CONFIG_RTC_DRV_RK808=y
|
||||
CONFIG_RTC_DRV_ROCKCHIP=y
|
||||
CONFIG_DMADEVICES=y
|
||||
CONFIG_ROCKCHIP_DMA=y
|
||||
CONFIG_DMABUF_HEAPS=y
|
||||
CONFIG_DMABUF_HEAPS_SYSTEM=y
|
||||
CONFIG_DMABUF_HEAPS_ROCKCHIP=y
|
||||
CONFIG_DMABUF_HEAPS_ROCKCHIP_CMA_HEAP=y
|
||||
CONFIG_DMABUF_HEAPS_ROCKCHIP_CMA_ALIGNMENT=0
|
||||
CONFIG_DMABUF_RK_HEAPS_DEBUG=y
|
||||
# CONFIG_VIRTIO_MENU is not set
|
||||
# CONFIG_VHOST_MENU is not set
|
||||
CONFIG_STAGING=y
|
||||
CONFIG_COMMON_CLK_PROCFS=y
|
||||
CONFIG_COMMON_CLK_RK808=y
|
||||
CONFIG_ROCKCHIP_CLK_OUT=y
|
||||
CONFIG_ROCKCHIP_CLK_PVTPLL=y
|
||||
# CONFIG_ARM_ARCH_TIMER_EVTSTREAM is not set
|
||||
CONFIG_ROCKCHIP_IOMMU=y
|
||||
CONFIG_CPU_RV1126B=y
|
||||
CONFIG_ROCKCHIP_AMP=y
|
||||
CONFIG_ROCKCHIP_CPUINFO=y
|
||||
CONFIG_ROCKCHIP_OPP=y
|
||||
CONFIG_ROCKCHIP_PM_DOMAINS=y
|
||||
CONFIG_ROCKCHIP_SYSTEM_MONITOR=y
|
||||
CONFIG_ROCKCHIP_VENDOR_STORAGE=y
|
||||
CONFIG_FIQ_DEBUGGER=y
|
||||
CONFIG_FIQ_DEBUGGER_NO_SLEEP=y
|
||||
CONFIG_FIQ_DEBUGGER_CONSOLE=y
|
||||
CONFIG_FIQ_DEBUGGER_CONSOLE_DEFAULT_ENABLE=y
|
||||
CONFIG_RK_CONSOLE_THREAD=y
|
||||
CONFIG_ROCKCHIP_DEBUG=y
|
||||
CONFIG_ROCKCHIP_MINI_KERNEL=y
|
||||
CONFIG_ROCKCHIP_NPOR_POWERGOOD=y
|
||||
CONFIG_RK_CMA_PROCFS=y
|
||||
CONFIG_RK_DMABUF_PROCFS=y
|
||||
CONFIG_RK_MEMBLOCK_PROCFS=y
|
||||
CONFIG_PM_DEVFREQ=y
|
||||
CONFIG_DEVFREQ_GOV_SIMPLE_ONDEMAND=y
|
||||
CONFIG_DEVFREQ_GOV_USERSPACE=y
|
||||
CONFIG_EXTCON=y
|
||||
CONFIG_IIO=y
|
||||
CONFIG_ROCKCHIP_SARADC=y
|
||||
CONFIG_INV_ICM42670_SPI=y
|
||||
CONFIG_PWM=y
|
||||
CONFIG_PWM_ROCKCHIP=y
|
||||
CONFIG_PHY_ROCKCHIP_CSI2_DPHY=y
|
||||
CONFIG_PHY_ROCKCHIP_INNO_USB2=y
|
||||
CONFIG_PHY_ROCKCHIP_INNO_DSIDPHY=y
|
||||
CONFIG_PHY_ROCKCHIP_NANENG_COMBO_PHY=y
|
||||
CONFIG_NVMEM_ROCKCHIP_OTP=y
|
||||
CONFIG_ROCKCHIP_RKNPU=y
|
||||
# CONFIG_ROCKCHIP_RKNPU_DEBUG_FS is not set
|
||||
CONFIG_ROCKCHIP_RKNPU_PROC_FS=y
|
||||
CONFIG_ROCKCHIP_RKNPU_DMA_HEAP=y
|
||||
CONFIG_EXT4_FS=y
|
||||
CONFIG_EXPORTFS_BLOCK_OPS=y
|
||||
# CONFIG_DNOTIFY is not set
|
||||
CONFIG_VFAT_FS=y
|
||||
CONFIG_TMPFS=y
|
||||
CONFIG_JFFS2_FS=y
|
||||
CONFIG_JFFS2_COMPRESSION_OPTIONS=y
|
||||
# CONFIG_JFFS2_RTIME is not set
|
||||
CONFIG_UBIFS_FS=y
|
||||
CONFIG_UBIFS_FS_ADVANCED_COMPR=y
|
||||
# CONFIG_UBIFS_FS_ZSTD is not set
|
||||
CONFIG_SQUASHFS=y
|
||||
# CONFIG_SQUASHFS_ZLIB is not set
|
||||
CONFIG_SQUASHFS_XZ=y
|
||||
CONFIG_SQUASHFS_4K_DEVBLK_SIZE=y
|
||||
CONFIG_NFS_FS=y
|
||||
CONFIG_NFS_V3_ACL=y
|
||||
CONFIG_NFS_V4=y
|
||||
CONFIG_NLS_CODEPAGE_437=y
|
||||
CONFIG_NLS_ISO8859_1=y
|
||||
# CONFIG_XZ_DEC_X86 is not set
|
||||
# CONFIG_XZ_DEC_POWERPC is not set
|
||||
# CONFIG_XZ_DEC_IA64 is not set
|
||||
# CONFIG_XZ_DEC_SPARC is not set
|
||||
CONFIG_DMA_CMA=y
|
||||
CONFIG_CMA_SIZE_MBYTES=0
|
||||
CONFIG_PRINTK_TIME=y
|
||||
CONFIG_PRINTK_TIME_FROM_ARM_ARCH_TIMER=y
|
||||
# CONFIG_DEBUG_MISC is not set
|
||||
CONFIG_DEBUG_INFO_DWARF_TOOLCHAIN_DEFAULT=y
|
||||
CONFIG_DEBUG_FS=y
|
||||
# CONFIG_SLUB_DEBUG is not set
|
||||
CONFIG_PANIC_ON_OOPS=y
|
||||
CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC=y
|
||||
CONFIG_HARDLOCKUP_DETECTOR=y
|
||||
CONFIG_BOOTPARAM_HARDLOCKUP_PANIC=y
|
||||
# CONFIG_DETECT_HUNG_TASK is not set
|
||||
# CONFIG_SCHED_DEBUG is not set
|
||||
# CONFIG_RCU_TRACE is not set
|
||||
# CONFIG_FTRACE is not set
|
||||
# CONFIG_RUNTIME_TESTING_MENU is not set
|
||||
@@ -245,6 +245,9 @@ static void __init free_highpages(void)
|
||||
phys_addr_t range_start, range_end;
|
||||
u64 i;
|
||||
|
||||
if (IS_ENABLED(CONFIG_ROCKCHIP_THUNDER_BOOT_DEFER_FREE_MEMBLOCK))
|
||||
return;
|
||||
|
||||
/* set highmem page free */
|
||||
for_each_free_mem_range(i, NUMA_NO_NODE, MEMBLOCK_NONE,
|
||||
&range_start, &range_end, NULL) {
|
||||
|
||||
@@ -1552,6 +1552,44 @@ u32 rk628_hdmirx_get_tmdsclk_cnt(struct rk628 *rk628)
|
||||
}
|
||||
EXPORT_SYMBOL(rk628_hdmirx_get_tmdsclk_cnt);
|
||||
|
||||
struct rk628_timings {
|
||||
int vic;
|
||||
int hactive;
|
||||
int hfp;
|
||||
int hsync;
|
||||
int hbp;
|
||||
int htotal;
|
||||
int vactive;
|
||||
int vfp;
|
||||
int vsync;
|
||||
int vbp;
|
||||
int vtotal;
|
||||
int clock;
|
||||
};
|
||||
|
||||
static const struct rk628_timings pre_timing[] = {
|
||||
{ 2, 720, 16, 62, 60, 858, 480, 9, 6, 30, 525, 27000000 },
|
||||
{ 3, 720, 16, 62, 60, 858, 480, 9, 6, 30, 525, 27000000 },
|
||||
{ 4, 1280, 110, 40, 220, 1650, 720, 5, 5, 20, 750, 74250000},
|
||||
{ 16, 1920, 88, 44, 148, 2200, 1080, 4, 5, 36, 1125, 148500000 },
|
||||
{ 19, 1280, 440, 40, 220, 1980, 720, 5, 5, 20, 750, 74250000},
|
||||
{ 31, 1920, 528, 44, 148, 2640, 1080, 4, 5, 36, 1125, 148500000},
|
||||
{ 32, 1920, 638, 44, 148, 2750, 1080, 4, 5, 36, 1125, 74250000},
|
||||
{ 33, 1920, 528, 44, 148, 2640, 1080, 4, 5, 36, 1125, 74250000},
|
||||
{ 34, 1920, 88, 44, 148, 2200, 1080, 4, 5, 36, 1125, 74250000},
|
||||
{ 62, 1280, 1760, 40, 220, 3300, 720, 5, 5, 20, 750, 74250000},
|
||||
{ 93, 3840, 1276, 88, 296, 5500, 2160, 8, 10, 72, 2250, 297000000 },
|
||||
{ 94, 3840, 1056, 88, 296, 5280, 2160, 8, 10, 72, 2250, 297000000 },
|
||||
{ 95, 3840, 176, 88, 296, 4400, 2160, 8, 10, 72, 2250, 297000000 },
|
||||
{ 96, 3840, 1056, 88, 296, 5280, 2160, 8, 10, 72, 2250, 594000000 },
|
||||
{ 97, 3840, 176, 88, 296, 4400, 2160, 8, 10, 72, 2250, 594000000 },
|
||||
{ 103, 3840, 1276, 88, 296, 5500, 2160, 8, 10, 72, 2250, 297000000 },
|
||||
{ 104, 3840, 1056, 88, 296, 5280, 2160, 8, 10, 72, 2250, 297000000 },
|
||||
{ 105, 3840, 176, 88, 296, 4400, 2160, 8, 10, 72, 2250, 297000000 },
|
||||
{ 106, 3840, 1056, 88, 296, 5280, 2160, 8, 10, 72, 2250, 594000000 },
|
||||
{ 107, 3840, 176, 88, 296, 4400, 2160, 8, 10, 72, 2250, 594000000 },
|
||||
};
|
||||
|
||||
static int rk628_hdmirx_read_timing(struct rk628 *rk628,
|
||||
struct v4l2_dv_timings *timings)
|
||||
{
|
||||
@@ -1564,6 +1602,7 @@ static int rk628_hdmirx_read_timing(struct rk628 *rk628,
|
||||
u64 tmp_data;
|
||||
u8 video_fmt, vic, color_range, color_space;
|
||||
u32 format;
|
||||
int i, match = 0;
|
||||
|
||||
memset(timings, 0, sizeof(struct v4l2_dv_timings));
|
||||
timings->type = V4L2_DV_BT_656_1120;
|
||||
@@ -1574,55 +1613,6 @@ static int rk628_hdmirx_read_timing(struct rk628 *rk628,
|
||||
bt->interlaced = val & ILACE_STS ?
|
||||
V4L2_DV_INTERLACED : V4L2_DV_PROGRESSIVE;
|
||||
|
||||
rk628_i2c_read(rk628, HDMI_RX_MD_HACT_PX, &val);
|
||||
hact = val & 0xffff;
|
||||
rk628_i2c_read(rk628, HDMI_RX_MD_VAL, &val);
|
||||
vact = val & 0xffff;
|
||||
rk628_i2c_read(rk628, HDMI_RX_MD_HT1, &val);
|
||||
htotal = (val >> 16) & 0xffff;
|
||||
rk628_i2c_read(rk628, HDMI_RX_MD_VTL, &val);
|
||||
vtotal = val & 0xffff;
|
||||
rk628_i2c_read(rk628, HDMI_RX_MD_HT1, &val);
|
||||
hofs_pix = val & 0xffff;
|
||||
rk628_i2c_read(rk628, HDMI_RX_MD_VOL, &val);
|
||||
vbp = (val & 0xffff) + 1;
|
||||
|
||||
tmdsclk_cnt = rk628_hdmirx_get_tmdsclk_cnt(rk628);
|
||||
tmp_data = tmdsclk_cnt;
|
||||
tmp_data = ((tmp_data * HDMIRX_MODETCLK_HZ) + HDMIRX_MODETCLK_CNT_NUM / 2);
|
||||
do_div(tmp_data, HDMIRX_MODETCLK_CNT_NUM);
|
||||
tmds_clk = tmp_data;
|
||||
if (!htotal || !vtotal || bt->interlaced || vtotal > 3000) {
|
||||
dev_err(rk628->dev, "timing err, %s htotal:%d, vtotal:%d\n",
|
||||
bt->interlaced ? "interlaced is not supported," : "",
|
||||
htotal, vtotal);
|
||||
goto TIMING_ERR;
|
||||
}
|
||||
if (rk628->version >= RK628F_VERSION)
|
||||
fps = tmds_clk / (htotal * vtotal);
|
||||
else
|
||||
fps = (tmds_clk + (htotal * vtotal) / 2) / (htotal * vtotal);
|
||||
|
||||
rk628_i2c_read(rk628, HDMI_RX_MD_HT0, &val);
|
||||
modetclk_cnt_hs = val & 0xffff;
|
||||
hs = (tmdsclk_cnt * modetclk_cnt_hs + HDMIRX_MODETCLK_CNT_NUM / 2) /
|
||||
HDMIRX_MODETCLK_CNT_NUM;
|
||||
|
||||
rk628_i2c_read(rk628, HDMI_RX_MD_VSC, &val);
|
||||
modetclk_cnt_vs = val & 0xffff;
|
||||
vs = (tmdsclk_cnt * modetclk_cnt_vs + HDMIRX_MODETCLK_CNT_NUM / 2) /
|
||||
HDMIRX_MODETCLK_CNT_NUM;
|
||||
vs = (vs + htotal / 2) / htotal;
|
||||
|
||||
if ((hofs_pix < hs) || (htotal < (hact + hofs_pix)) ||
|
||||
(vtotal < (vact + vs + vbp)) || !vs) {
|
||||
dev_err(rk628->dev, "timing err, total:%dx%d, act:%dx%d, hofs:%d, hs:%d, vs:%d, vbp:%d\n",
|
||||
htotal, vtotal, hact, vact, hofs_pix, hs, vs, vbp);
|
||||
goto TIMING_ERR;
|
||||
}
|
||||
hbp = hofs_pix - hs;
|
||||
hfp = htotal - hact - hofs_pix;
|
||||
vfp = vtotal - vact - vs - vbp;
|
||||
|
||||
rk628_i2c_read(rk628, HDMI_RX_PDEC_AVI_PB, &val);
|
||||
vic = (val & VID_IDENT_CODE_MASK) >> 24;
|
||||
@@ -1637,28 +1627,101 @@ static int rk628_hdmirx_read_timing(struct rk628 *rk628,
|
||||
rk628->color_space = color_space;
|
||||
rk628_i2c_read(rk628, HDMI_RX_PDEC_STS, &val);
|
||||
rk628->dvi_mode = val & DVI_DET;
|
||||
if (video_fmt == BUS_FMT_YUV420) {
|
||||
//format:color depth, 5: 10bit, 4: 8bit
|
||||
if (format == 5) {
|
||||
htotal = htotal * 2 * 8 / 10;
|
||||
hact = hact * 2 * 8 / 10;
|
||||
hfp = hfp * 2 * 8 / 10;
|
||||
hbp = hbp * 2 * 8 / 10;
|
||||
hs = hs * 2 * 8 / 10;
|
||||
} else {
|
||||
htotal *= 2;
|
||||
hact *= 2;
|
||||
hfp *= 2;
|
||||
hbp *= 2;
|
||||
hs *= 2;
|
||||
|
||||
for (i = 0; vic && i < ARRAY_SIZE(pre_timing); i++) {
|
||||
if (vic == pre_timing[i].vic) {
|
||||
hact = pre_timing[i].hactive;
|
||||
hfp = pre_timing[i].hfp;
|
||||
hs = pre_timing[i].hsync;
|
||||
hbp = pre_timing[i].hbp;
|
||||
htotal = pre_timing[i].htotal;
|
||||
vact = pre_timing[i].vactive;
|
||||
vfp = pre_timing[i].vfp;
|
||||
vs = pre_timing[i].vsync;
|
||||
vbp = pre_timing[i].vbp;
|
||||
vtotal = pre_timing[i].vtotal;
|
||||
tmds_clk = pre_timing[i].clock;
|
||||
match = 1;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
rk628_dbg(rk628, "cnt_num:%d, tmds_cnt:%d, hs_cnt:%d, vs_cnt:%d, hofs:%d\n",
|
||||
HDMIRX_MODETCLK_CNT_NUM, tmdsclk_cnt, modetclk_cnt_hs, modetclk_cnt_vs, hofs_pix);
|
||||
if (!match) {
|
||||
rk628_i2c_read(rk628, HDMI_RX_MD_HACT_PX, &val);
|
||||
hact = val & 0xffff;
|
||||
rk628_i2c_read(rk628, HDMI_RX_MD_VAL, &val);
|
||||
vact = val & 0xffff;
|
||||
rk628_i2c_read(rk628, HDMI_RX_MD_HT1, &val);
|
||||
htotal = (val >> 16) & 0xffff;
|
||||
rk628_i2c_read(rk628, HDMI_RX_MD_VTL, &val);
|
||||
vtotal = val & 0xffff;
|
||||
rk628_i2c_read(rk628, HDMI_RX_MD_HT1, &val);
|
||||
hofs_pix = val & 0xffff;
|
||||
rk628_i2c_read(rk628, HDMI_RX_MD_VOL, &val);
|
||||
vbp = (val & 0xffff) + 1;
|
||||
|
||||
tmdsclk_cnt = rk628_hdmirx_get_tmdsclk_cnt(rk628);
|
||||
tmp_data = tmdsclk_cnt;
|
||||
tmp_data = ((tmp_data * HDMIRX_MODETCLK_HZ) + HDMIRX_MODETCLK_CNT_NUM / 2);
|
||||
do_div(tmp_data, HDMIRX_MODETCLK_CNT_NUM);
|
||||
tmds_clk = tmp_data;
|
||||
if (!htotal || !vtotal || bt->interlaced || vtotal > 3000) {
|
||||
dev_err(rk628->dev, "timing err, %s htotal:%d, vtotal:%d\n",
|
||||
bt->interlaced ? "interlaced is not supported," : "",
|
||||
htotal, vtotal);
|
||||
goto TIMING_ERR;
|
||||
}
|
||||
|
||||
rk628_i2c_read(rk628, HDMI_RX_MD_HT0, &val);
|
||||
modetclk_cnt_hs = val & 0xffff;
|
||||
hs = (tmdsclk_cnt * modetclk_cnt_hs + HDMIRX_MODETCLK_CNT_NUM / 2) /
|
||||
HDMIRX_MODETCLK_CNT_NUM;
|
||||
|
||||
rk628_i2c_read(rk628, HDMI_RX_MD_VSC, &val);
|
||||
modetclk_cnt_vs = val & 0xffff;
|
||||
vs = (tmdsclk_cnt * modetclk_cnt_vs + HDMIRX_MODETCLK_CNT_NUM / 2) /
|
||||
HDMIRX_MODETCLK_CNT_NUM;
|
||||
vs = (vs + htotal / 2) / htotal;
|
||||
|
||||
if ((hofs_pix < hs) || (htotal < (hact + hofs_pix)) ||
|
||||
(vtotal < (vact + vs + vbp)) || !vs) {
|
||||
dev_err(rk628->dev, "timing err, total:%dx%d, act:%dx%d, hofs:%d, hs:%d, vs:%d, vbp:%d\n",
|
||||
htotal, vtotal, hact, vact, hofs_pix, hs, vs, vbp);
|
||||
goto TIMING_ERR;
|
||||
}
|
||||
hbp = hofs_pix - hs;
|
||||
hfp = htotal - hact - hofs_pix;
|
||||
vfp = vtotal - vact - vs - vbp;
|
||||
|
||||
if (video_fmt == BUS_FMT_YUV420) {
|
||||
//format:color depth, 5: 10bit, 4: 8bit
|
||||
if (format == 5) {
|
||||
htotal = htotal * 2 * 8 / 10;
|
||||
hact = hact * 2 * 8 / 10;
|
||||
hfp = hfp * 2 * 8 / 10;
|
||||
hbp = hbp * 2 * 8 / 10;
|
||||
hs = hs * 2 * 8 / 10;
|
||||
} else {
|
||||
htotal *= 2;
|
||||
hact *= 2;
|
||||
hfp *= 2;
|
||||
hbp *= 2;
|
||||
hs *= 2;
|
||||
}
|
||||
}
|
||||
|
||||
rk628_dbg(rk628, "cnt_num:%d, tmds_cnt:%d, hs_cnt:%d, vs_cnt:%d, hofs:%d\n",
|
||||
HDMIRX_MODETCLK_CNT_NUM, tmdsclk_cnt, modetclk_cnt_hs,
|
||||
modetclk_cnt_vs, hofs_pix);
|
||||
}
|
||||
|
||||
rk628_dbg(rk628, "get current aviif: vic:%d, color_range: %s, color_space %s",
|
||||
vic, bus_color_range_str[color_range], bus_color_space_str[color_space]);
|
||||
|
||||
if (rk628->version >= RK628F_VERSION)
|
||||
fps = tmds_clk / (htotal * vtotal);
|
||||
else
|
||||
fps = (tmds_clk + (htotal * vtotal) / 2) / (htotal * vtotal);
|
||||
bt->width = hact;
|
||||
bt->height = vact;
|
||||
bt->hfrontporch = hfp;
|
||||
@@ -1677,12 +1740,14 @@ static int rk628_hdmirx_read_timing(struct rk628 *rk628,
|
||||
bt->il_vsync = bt->vsync + 1;
|
||||
bt->pixelclock /= 2;
|
||||
}
|
||||
if (video_fmt == BUS_FMT_YUV420) {
|
||||
if (format == 5) {
|
||||
bt->pixelclock = bt->pixelclock * 8 * 2;
|
||||
do_div(bt->pixelclock, 10);
|
||||
} else {
|
||||
bt->pixelclock *= 2;
|
||||
if (!match) {
|
||||
if (video_fmt == BUS_FMT_YUV420) {
|
||||
if (format == 5) {
|
||||
bt->pixelclock = bt->pixelclock * 8 * 2;
|
||||
do_div(bt->pixelclock, 10);
|
||||
} else {
|
||||
bt->pixelclock *= 2;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
@@ -4302,6 +4302,31 @@ static int rkcif_dvp_get_input_yuv_order(struct rkcif_stream *stream)
|
||||
return mask;
|
||||
}
|
||||
|
||||
static int rkcif_dvp_get_input_yuv_order_rk3576(struct rkcif_stream *stream)
|
||||
{
|
||||
unsigned int mask;
|
||||
const struct cif_input_fmt *fmt = stream->cif_fmt_in;
|
||||
|
||||
switch (fmt->mbus_code) {
|
||||
case MEDIA_BUS_FMT_UYVY8_2X8:
|
||||
mask = CSI_YUV_INPUT_ORDER_UYVY;
|
||||
break;
|
||||
case MEDIA_BUS_FMT_VYUY8_2X8:
|
||||
mask = CSI_YUV_INPUT_ORDER_VYUY;
|
||||
break;
|
||||
case MEDIA_BUS_FMT_YUYV8_2X8:
|
||||
mask = CSI_YUV_INPUT_ORDER_YUYV;
|
||||
break;
|
||||
case MEDIA_BUS_FMT_YVYU8_2X8:
|
||||
mask = CSI_YUV_INPUT_ORDER_YVYU;
|
||||
break;
|
||||
default:
|
||||
mask = CSI_YUV_INPUT_ORDER_UYVY;
|
||||
break;
|
||||
}
|
||||
return mask;
|
||||
}
|
||||
|
||||
static int rkcif_csi_get_output_type_mask(struct rkcif_stream *stream)
|
||||
{
|
||||
unsigned int mask;
|
||||
@@ -7834,11 +7859,12 @@ static int rkcif_stream_start(struct rkcif_stream *stream, unsigned int mode)
|
||||
val &= ~CIF_HIGH_ALIGN_RK3588;
|
||||
} else {
|
||||
out_fmt_mask = rkcif_dvp_get_output_type_mask_rk3576(stream);
|
||||
in_fmt_yuv_order = rkcif_dvp_get_input_yuv_order_rk3576(stream);
|
||||
val = vsync_pol | href_pol
|
||||
| inputmode
|
||||
| yc_swap
|
||||
| out_fmt_mask
|
||||
| stream->cif_fmt_in->dvp_fmt_val
|
||||
| in_fmt_yuv_order
|
||||
| multi_id_en
|
||||
| xfer_mode
|
||||
| multi_id_sel | multi_id_mode
|
||||
|
||||
@@ -102,7 +102,7 @@ static int buf_alloc(struct file *file, struct rkfec_buf *info)
|
||||
return -ENOMEM;
|
||||
#if IS_LINUX_VERSION_AT_LEAST_6_1
|
||||
init_vb2(ofl, buf);
|
||||
mem = ops->alloc(&buf->vb, hw->dev, info->size);
|
||||
mem = ops->alloc(&buf->vb, hw->dev, size);
|
||||
#else
|
||||
mem = ops->alloc(hw->dev, DMA_ATTR_NO_KERNEL_MAPPING, size,
|
||||
DMA_BIDIRECTIONAL, GFP_KERNEL | GFP_DMA32);
|
||||
@@ -141,7 +141,7 @@ static int buf_alloc(struct file *file, struct rkfec_buf *info)
|
||||
list_add_tail(&buf->list, &ofl->list);
|
||||
mutex_unlock(&hw->dev_lock);
|
||||
v4l2_dbg(1, rkfec_debug, &ofl->v4l2_dev, "%s file:%p, fd:%d dbuf:%p size %d\n",
|
||||
__func__, file, fd, dbuf, info->size);
|
||||
__func__, file, fd, dbuf, size);
|
||||
return 0;
|
||||
|
||||
err_dmabuf_fd:
|
||||
|
||||
@@ -1727,11 +1727,15 @@ static int rkvpss_ofl_run(struct rkvpss_offline_dev *ofl,
|
||||
if (!hw->is_ofl_ch[i])
|
||||
continue;
|
||||
mask |= (RKVPSS_ISP2VPSS_CHN0_SEL(3) << i * 2);
|
||||
if (hw->is_ofl_cmsc)
|
||||
mask |= RKVPSS_ISP2VPSS_ONLINE2_CMSC_EN;
|
||||
if (cfg->output[i].enable)
|
||||
val |= (RKVPSS_ISP2VPSS_CHN0_SEL(1) << i * 2);
|
||||
}
|
||||
if (hw->is_ofl_cmsc) {
|
||||
val |= RKVPSS_ISP2VPSS_ONLINE2_CMSC_EN;
|
||||
mask |= RKVPSS_ISP2VPSS_ONLINE2_CMSC_EN;
|
||||
}
|
||||
val |= RKVPSS_ISP2VPSS_ONLINE2;
|
||||
mask |= RKVPSS_ISP2VPSS_ONLINE2;
|
||||
rkvpss_hw_set_bits(hw, RKVPSS_VPSS_ONLINE, mask, val);
|
||||
|
||||
update = 0;
|
||||
|
||||
@@ -1541,6 +1541,7 @@ static int rockchip_opp_set_config(struct device *dev, struct rockchip_opp_info
|
||||
struct clk *clk = NULL;
|
||||
const char *reg_names[] = {NULL, NULL, NULL};
|
||||
const char *clk_names[] = {NULL, NULL, NULL};
|
||||
int ret = 0;
|
||||
|
||||
if (clk_name) {
|
||||
clk = clk_get(dev, clk_name);
|
||||
@@ -1592,7 +1593,8 @@ static int rockchip_opp_set_config(struct device *dev, struct rockchip_opp_info
|
||||
info->opp_token = dev_pm_opp_set_config(dev, &config);
|
||||
if (info->opp_token < 0) {
|
||||
dev_err(dev, "failed to set opp config\n");
|
||||
return info->opp_token;
|
||||
ret = info->opp_token;
|
||||
goto err;
|
||||
}
|
||||
|
||||
/*
|
||||
@@ -1602,10 +1604,15 @@ static int rockchip_opp_set_config(struct device *dev, struct rockchip_opp_info
|
||||
*/
|
||||
if (rockchip_opp_set_regulator_helper(dev, info)) {
|
||||
dev_err(dev, "failed to set opp regulator helper\n");
|
||||
return -EINVAL;
|
||||
dev_pm_opp_clear_config(info->opp_token);
|
||||
info->opp_token = 0;
|
||||
ret = -EINVAL;
|
||||
}
|
||||
|
||||
return 0;
|
||||
err:
|
||||
kfree(config.supported_hw);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
void rockchip_opp_dvfs_lock(struct rockchip_opp_info *info)
|
||||
@@ -1778,6 +1785,7 @@ EXPORT_SYMBOL(rockchip_init_opp_info);
|
||||
void rockchip_uninit_opp_info(struct device *dev, struct rockchip_opp_info *info)
|
||||
{
|
||||
dev_pm_opp_clear_config(info->opp_token);
|
||||
info->opp_token = 0;
|
||||
}
|
||||
EXPORT_SYMBOL(rockchip_uninit_opp_info);
|
||||
|
||||
|
||||
@@ -8,7 +8,7 @@
|
||||
#include <linux/dma-buf.h>
|
||||
#include <linux/rk-isp2-config.h>
|
||||
|
||||
#define ROCKIT_BUF_NUM_MAX 5
|
||||
#define ROCKIT_BUF_NUM_MAX 20
|
||||
#define ROCKIT_ISP_NUM_MAX 3
|
||||
#define ROCKIT_STREAM_NUM_MAX 12
|
||||
|
||||
|
||||
@@ -370,6 +370,14 @@ extern void __putback_isolated_page(struct page *page, unsigned int order,
|
||||
int mt);
|
||||
extern void memblock_free_pages(struct page *page, unsigned long pfn,
|
||||
unsigned int order);
|
||||
#ifdef CONFIG_ROCKCHIP_THUNDER_BOOT_DEFER_FREE_MEMBLOCK
|
||||
extern void __init rk_free_pages_core(struct page *page, unsigned int order);
|
||||
extern unsigned long __init rk_deferred_init_pages(struct zone *zone,
|
||||
unsigned long pfn,
|
||||
unsigned long end_pfn);
|
||||
extern bool __meminit rk_defer_init_hpages(int nid, unsigned long zone_idx,
|
||||
unsigned long pfn, unsigned long end_pfn);
|
||||
#endif
|
||||
extern void __free_pages_core(struct page *page, unsigned int order);
|
||||
extern void prep_compound_page(struct page *page, unsigned int order);
|
||||
extern void post_alloc_hook(struct page *page, unsigned int order,
|
||||
|
||||
@@ -124,7 +124,19 @@ static int __init early_defer_free_block_size(char *p)
|
||||
}
|
||||
|
||||
early_param("defer_free_block_size", early_defer_free_block_size);
|
||||
#endif
|
||||
|
||||
/* deferred highpage stuff */
|
||||
struct rk_defered_highpage_info {
|
||||
unsigned long pfn_start;
|
||||
unsigned long pfn_end;
|
||||
struct zone *zone;
|
||||
};
|
||||
|
||||
#define RK_DHPI_NUM_MAX 3
|
||||
|
||||
static struct rk_defered_highpage_info rk_dhpi[RK_DHPI_NUM_MAX];
|
||||
static int rk_dhpi_num;
|
||||
#endif /* CONFIG_ROCKCHIP_THUNDER_BOOT_DEFER_FREE_MEMBLOCK */
|
||||
|
||||
unsigned long max_low_pfn;
|
||||
unsigned long min_low_pfn;
|
||||
@@ -2072,9 +2084,86 @@ static void __init __free_pages_memory(unsigned long start, unsigned long end)
|
||||
}
|
||||
|
||||
#ifdef CONFIG_ROCKCHIP_THUNDER_BOOT_DEFER_FREE_MEMBLOCK
|
||||
static void __init rk_free_highpages(void)
|
||||
{
|
||||
#ifdef CONFIG_HIGHMEM
|
||||
unsigned long max_low = max_low_pfn;
|
||||
phys_addr_t range_start, range_end;
|
||||
u64 i;
|
||||
|
||||
/* set highmem page free */
|
||||
for_each_free_mem_range(i, NUMA_NO_NODE, MEMBLOCK_NONE,
|
||||
&range_start, &range_end, NULL) {
|
||||
unsigned long start = PFN_UP(range_start);
|
||||
unsigned long end = PFN_DOWN(range_end);
|
||||
|
||||
/* Ignore complete lowmem entries */
|
||||
if (end <= max_low)
|
||||
continue;
|
||||
|
||||
/* Truncate partial highmem entries */
|
||||
if (start < max_low)
|
||||
start = max_low;
|
||||
|
||||
while (start < end) {
|
||||
int order;
|
||||
|
||||
order = min(MAX_ORDER - 1UL, __ffs(start));
|
||||
|
||||
while (start + (1UL << order) > end)
|
||||
order--;
|
||||
|
||||
rk_free_pages_core(pfn_to_page(start), order);
|
||||
start += (1UL << order);
|
||||
|
||||
cond_resched();
|
||||
}
|
||||
}
|
||||
#endif
|
||||
}
|
||||
|
||||
bool __meminit rk_defer_init_hpages(int nid, unsigned long zone_idx,
|
||||
unsigned long pfn, unsigned long end_pfn)
|
||||
{
|
||||
struct pglist_data *pdata = NODE_DATA(nid);
|
||||
struct zone *zone = &pdata->node_zones[zone_idx];
|
||||
|
||||
if (rk_dhpi_num >= RK_DHPI_NUM_MAX) {
|
||||
pr_err("too much deferred page zone\n");
|
||||
return false;
|
||||
}
|
||||
|
||||
if (strstr(zone->name, "HighMem")) {
|
||||
pr_debug("%s, zone : %s, pfn[0x%lx-0x%lx]\n", __func__,
|
||||
zone->name, pfn, end_pfn);
|
||||
rk_dhpi[rk_dhpi_num].pfn_start = pfn;
|
||||
rk_dhpi[rk_dhpi_num].pfn_end = end_pfn;
|
||||
rk_dhpi[rk_dhpi_num].zone = zone;
|
||||
rk_dhpi_num++;
|
||||
|
||||
return true;
|
||||
}
|
||||
return false;
|
||||
}
|
||||
|
||||
int __init defer_free_memblock(void *unused)
|
||||
{
|
||||
int i;
|
||||
unsigned long nr_pages = 0;
|
||||
|
||||
pr_debug("%s, rk_dhpi_num = %d\n", __func__, rk_dhpi_num);
|
||||
|
||||
for (i = 0; i < rk_dhpi_num; i++) {
|
||||
struct zone *zone = rk_dhpi[i].zone;
|
||||
unsigned long start_pfn = rk_dhpi[i].pfn_start;
|
||||
unsigned long end_pfn = rk_dhpi[i].pfn_end;
|
||||
|
||||
pr_info("%s, zone : %s, pfn[0x%lx-0x%lx]\n", __func__,
|
||||
zone->name, start_pfn, end_pfn);
|
||||
nr_pages += rk_deferred_init_pages(zone, start_pfn, end_pfn);
|
||||
}
|
||||
|
||||
pr_debug("%s, deferred_nr_page = 0x%lx\n", __func__, nr_pages);
|
||||
|
||||
for (i = 0; i < db_count; i++) {
|
||||
pr_debug("%s: start = %ld, end = %ld\n",
|
||||
@@ -2091,9 +2180,12 @@ int __init defer_free_memblock(void *unused)
|
||||
db[i].defer_end >> (20 - PAGE_SHIFT),
|
||||
totalram_pages() >> (20 - PAGE_SHIFT));
|
||||
}
|
||||
|
||||
rk_free_highpages();
|
||||
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
#endif /* CONFIG_ROCKCHIP_THUNDER_BOOT_DEFER_FREE_MEMBLOCK */
|
||||
|
||||
static unsigned long __init __free_memory_core(phys_addr_t start,
|
||||
phys_addr_t end)
|
||||
|
||||
@@ -1871,6 +1871,43 @@ void __init memblock_free_pages(struct page *page, unsigned long pfn,
|
||||
__free_pages_core(page, order);
|
||||
}
|
||||
|
||||
#ifdef CONFIG_ROCKCHIP_THUNDER_BOOT_DEFER_FREE_MEMBLOCK
|
||||
void __init rk_free_pages_core(struct page *page, unsigned int order)
|
||||
{
|
||||
__free_pages_core(page, order);
|
||||
totalram_pages_add(1 << order);
|
||||
#ifdef CONFIG_HIGHMEM
|
||||
if (PageHighMem(page))
|
||||
totalhigh_pages_add(1 << order);
|
||||
#endif
|
||||
}
|
||||
|
||||
unsigned long __init rk_deferred_init_pages(struct zone *zone,
|
||||
unsigned long pfn,
|
||||
unsigned long end_pfn)
|
||||
{
|
||||
int nid = zone_to_nid(zone);
|
||||
unsigned long nr_pages = 0;
|
||||
int zid = zone_idx(zone);
|
||||
struct page *page = NULL;
|
||||
|
||||
for (; pfn < end_pfn; pfn++) {
|
||||
if (!page || pageblock_aligned(pfn))
|
||||
page = pfn_to_page(pfn);
|
||||
else
|
||||
page++;
|
||||
|
||||
__init_single_page(page, pfn, zid, nid, true);
|
||||
nr_pages++;
|
||||
|
||||
/* Call cond_resched() only once every 8 pages */
|
||||
if ((nr_pages & 7) == 0)
|
||||
cond_resched();
|
||||
}
|
||||
return (nr_pages);
|
||||
}
|
||||
#endif /* CONFIG_ROCKCHIP_THUNDER_BOOT_DEFER_FREE_MEMBLOCK */
|
||||
|
||||
/*
|
||||
* Check that the whole (or subset of) a pageblock given by the interval of
|
||||
* [start_pfn, end_pfn) is valid and within the same zone, before scanning it
|
||||
@@ -6987,6 +7024,11 @@ void __meminit memmap_init_range(unsigned long size, int nid, unsigned long zone
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_ROCKCHIP_THUNDER_BOOT_DEFER_FREE_MEMBLOCK
|
||||
if (rk_defer_init_hpages(nid, zone, start_pfn, end_pfn))
|
||||
return;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_ROCKCHIP_THUNDER_BOOT
|
||||
/* Zero all page struct in advance */
|
||||
memset(pfn_to_page(start_pfn), 0, sizeof(struct page) * size);
|
||||
|
||||
Reference in New Issue
Block a user