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phy: rockchip-samsung-hdptx-hdmi: Remove phy/pll reset
These are ic debug reset, practically unusable. Change-Id: Ibc5817ccf9d17abf35d1ff32c2a047866ef1dd2f Signed-off-by: Algea Cao <algea.cao@rock-chips.com>
This commit is contained in:
@@ -719,13 +719,10 @@ struct rockchip_hdptx_phy {
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struct clk *dclk;
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unsigned long rate;
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struct reset_control *phy_reset;
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struct reset_control *apb_reset;
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struct reset_control *cmn_reset;
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struct reset_control *init_reset;
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struct reset_control *lane_reset;
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struct reset_control *ropll_reset;
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struct reset_control *lcpll_reset;
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bool earc_en;
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int count;
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@@ -990,11 +987,7 @@ static void hdptx_phy_disable(struct rockchip_hdptx_phy *hdptx)
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{
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u32 val;
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/* reset phy and apb, or phy locked flag may keep 1 */
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reset_control_assert(hdptx->phy_reset);
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udelay(20);
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reset_control_deassert(hdptx->phy_reset);
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/* reset apb, or phy locked flag may keep 1 */
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reset_control_assert(hdptx->apb_reset);
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udelay(20);
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reset_control_deassert(hdptx->apb_reset);
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@@ -1203,10 +1196,6 @@ static int hdptx_ropll_cmn_config(struct rockchip_hdptx_phy *hdptx, unsigned lon
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hdptx_pre_power_up(hdptx);
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reset_control_assert(hdptx->ropll_reset);
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udelay(20);
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reset_control_deassert(hdptx->ropll_reset);
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hdptx_grf_write(hdptx, GRF_HDPTX_CON0, LC_REF_CLK_SEL << 16);
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hdptx_write(hdptx, CMN_REG0008, 0x00);
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@@ -1480,14 +1469,6 @@ static int hdptx_lcpll_ropll_cmn_config(struct rockchip_hdptx_phy *hdptx, unsign
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hdptx_pre_power_up(hdptx);
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reset_control_assert(hdptx->ropll_reset);
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udelay(20);
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reset_control_deassert(hdptx->ropll_reset);
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reset_control_assert(hdptx->lcpll_reset);
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udelay(20);
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reset_control_deassert(hdptx->lcpll_reset);
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/* ROPLL input reference clock from LCPLL (cascade mode) */
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val = (LC_REF_CLK_SEL << 16) | LC_REF_CLK_SEL;
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hdptx_grf_write(hdptx, GRF_HDPTX_CON0, val);
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@@ -2271,13 +2252,6 @@ static int rockchip_hdptx_phy_probe(struct platform_device *pdev)
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goto err_regsmap;
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}
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hdptx->phy_reset = devm_reset_control_get(dev, "phy");
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if (IS_ERR(hdptx->phy_reset)) {
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ret = PTR_ERR(hdptx->phy_reset);
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dev_err(dev, "failed to get phy reset: %d\n", ret);
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goto err_regsmap;
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}
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hdptx->apb_reset = devm_reset_control_get(dev, "apb");
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if (IS_ERR(hdptx->apb_reset)) {
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ret = PTR_ERR(hdptx->apb_reset);
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@@ -2306,20 +2280,6 @@ static int rockchip_hdptx_phy_probe(struct platform_device *pdev)
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goto err_regsmap;
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}
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hdptx->ropll_reset = devm_reset_control_get(dev, "ropll");
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if (IS_ERR(hdptx->ropll_reset)) {
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ret = PTR_ERR(hdptx->ropll_reset);
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dev_err(dev, "failed to get ropll reset: %d\n", ret);
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goto err_regsmap;
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}
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hdptx->lcpll_reset = devm_reset_control_get(dev, "lcpll");
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if (IS_ERR(hdptx->lcpll_reset)) {
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ret = PTR_ERR(hdptx->lcpll_reset);
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dev_err(dev, "failed to get lcpll reset: %d\n", ret);
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goto err_regsmap;
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}
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hdptx->grf = syscon_regmap_lookup_by_phandle(np, "rockchip,grf");
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if (IS_ERR(hdptx->grf)) {
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ret = PTR_ERR(hdptx->grf);
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