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ARM: dts: rockchip: add hevc & vpu service for rk3036

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There is a combo of a HEVC decoder and a VPU1 decoder at rk3036.

Change-Id: Ia7174cc9e2f2d640a74271077bd62cc68f3482b4
Signed-off-by: Randy Li <randy.li@rock-chips.com>
This commit is contained in:
Randy Li
2017-10-27 11:04:58 +08:00
committed by Tao Huang
parent 3eddd5dd86
commit 923228a434
1 changed files with 50 additions and 0 deletions
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50
arch/arm/boot/dts/rk3036.dtsi
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@@ -186,12 +186,62 @@
status = "disabled";
};
vpu_service: vpu-service@10108400 {
compatible = "rockchip,sub";
reg = <0x10108400 0x400>;
dev_mode = <0>;
interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "irq_dec";
iommus = <&vpu_mmu>;
allocator = <1>;
};
vpu_mmu: iommu@10108800 {
compatible = "rockchip,iommu";
reg = <0x10108800 0x100>;
interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "vpu_mmu";
#iommu-cells = <0>;
status = "disabled";
};
hevc_service: hevc-service@1010c000 {
compatible = "rockchip,sub";
reg = <0x1010c000 0x400>;
dev_mode = <1>;
interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "irq_dec";
allocator = <1>;
iommus = <&hevc_mmu>;
};
hevc_mmu: iommu@1010c440 {
compatible = "rockchip,iommu";
reg = <0x1010c440 0x40>, <0x1010c480 0x40>;
interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "hevc_mmu";
#iommu-cells = <0>;
status = "disabled";
};
vpu_combo: vpu-combo {
compatible = "rockchip,vpu_combo";
rockchip,grf = <&grf>;
subcnt = <2>;
rockchip,sub = <&hevc_service>, <&vpu_service>;
mode_bit = <3>;
mode_ctrl = <0x144>;
clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>,
<&cru ACLK_HEVC>;
clock-names = "aclk_vcodec", "hclk_vcodec", "clk_core";
/* RK3036's vpu could not run higher than 300M */
assigned-clocks = <&cru ACLK_VCODEC>;
assigned-clock-rates = <297000000>;
assigned-clock-parents = <&cru PLL_GPLL>;
resets = <&cru SRST_VCODEC_A>, <&cru SRST_VCODEC_H>,
<&cru SRST_HEVC>;
reset-names = "video_a", "video_h", "video";
status = "disabled";
};
vop: vop@10118000 {