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clk: rockchip: rk3288: export PCLK_PD_PMU and PCLK_PD_ALIVE clock id

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Change-Id: Ie0550d9528367fa070328562fad2e597a5d6d7f7
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
This commit is contained in:
Elaine Zhang
2018-05-14 16:09:52 +08:00
committed by Tao Huang
parent 9f6d1e6688
commit 9322b4700a
2 changed files with 6 additions and 2 deletions
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4
drivers/clk/rockchip/clk-rk3288.c
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@@ -490,9 +490,9 @@ static struct rockchip_clk_branch rk3288_clk_branches[] __initdata = {
COMPOSITE_NOGATE(SCLK_VIP_OUT, "sclk_vip_out", mux_vip_out_p, 0,
RK3288_CLKSEL_CON(26), 15, 1, MFLAGS, 9, 5, DFLAGS),
DIV(0, "pclk_pd_alive", "gpll", 0,
DIV(PCLK_PD_ALIVE, "pclk_pd_alive", "gpll", 0,
RK3288_CLKSEL_CON(33), 8, 5, DFLAGS),
COMPOSITE_NOMUX(0, "pclk_pd_pmu", "gpll", CLK_IGNORE_UNUSED,
COMPOSITE_NOMUX(PCLK_PD_PMU, "pclk_pd_pmu", "gpll", CLK_IGNORE_UNUSED,
RK3288_CLKSEL_CON(33), 0, 5, DFLAGS,
RK3288_CLKGATE_CON(5), 8, GFLAGS),

4
include/dt-bindings/clock/rk3288-cru.h
View File

@@ -161,6 +161,10 @@
#define PCLK_EFUSE256 369
#define PCLK_EFUSE1024 370
#define PCLK_ISP_IN 371
#define PCLK_VIP 372
#define PCLK_VIP_IN 373
#define PCLK_PD_ALIVE 374
#define PCLK_PD_PMU 375
/* hclk gates */
#define HCLK_GPS 448