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phy: rockchip: inno_usb2: update phy tuning for rv1106 and rv1103

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1. Set different pre_emphasize strength for rv1106 and rv1103.
   - Set pre_emphasize strength to 0x03 for cpu verison_0;
   - Set pre_emphasize strength to 0x01 for cpu verison_1;

2. Bypass Squelch detector calibration to improve receiving
   sensitivity.
   - Before: E-17 248.7mv, E-16 112.6mv
   - After:  E-17 150mv,   E-16 98.8mv

Note:
E-17 and E-16 is on page 3 of the "USB 2.0 Electrical Compliance Test Specification"
https://usb.org/document-library/usb-20-electrical-compliance-test-specification-version-107

Signed-off-by: William Wu <william.wu@rock-chips.com>
Change-Id: I0d668b3d126583ada03d9675e0175f02537d915f
This commit is contained in:
William Wu
2022-07-01 17:39:38 +08:00
parent ee66b0c6b8
commit 970efca023
1 changed files with 11 additions and 2 deletions
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13
drivers/phy/rockchip/phy-rockchip-inno-usb2.c
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@@ -2650,8 +2650,13 @@ static int rv1106_usb2phy_tuning(struct rockchip_usb2phy *rphy)
/* Always enable pre-emphasis in SOF & EOP & chirp & non-chirp state */
phy_update_bits(rphy->phy_base + 0x30, GENMASK(2, 0), 0x07);
/* Set Tx HS pre_emphasize strength to 3'b010 */
phy_update_bits(rphy->phy_base + 0x40, GENMASK(5, 3), (0x02 << 3));
if (rockchip_get_cpu_version()) {
/* Set Tx HS pre_emphasize strength to 3'b001 */
phy_update_bits(rphy->phy_base + 0x40, GENMASK(5, 3), (0x01 << 3));
} else {
/* Set Tx HS pre_emphasize strength to 3'b011 */
phy_update_bits(rphy->phy_base + 0x40, GENMASK(5, 3), (0x03 << 3));
}
/* Set RX Squelch trigger point configure to 4'b0000(112.5 mV) */
phy_update_bits(rphy->phy_base + 0x64, GENMASK(6, 3), (0x00 << 3));
@@ -2665,6 +2670,10 @@ static int rv1106_usb2phy_tuning(struct rockchip_usb2phy *rphy)
/* Set Tx HS eye height tuning to 3'b011(462 mV)*/
phy_update_bits(rphy->phy_base + 0x124, GENMASK(4, 2), (0x03 << 2));
/* Bypass Squelch detector calibration */
phy_update_bits(rphy->phy_base + 0x1a4, GENMASK(7, 4), (0x01 << 4));
phy_update_bits(rphy->phy_base + 0x1b4, GENMASK(7, 4), (0x01 << 4));
return 0;
}