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phy: rockchip: naneng-combphy: Fix CTLE register setting error for rk3528

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Signed-off-by: Jianwei Zheng <jianwei.zheng@rock-chips.com>
Change-Id: I6a217c1b041f5962c500bb4d03f689ce54a42443
This commit is contained in:
Jianwei Zheng
2023-05-17 14:28:08 +08:00
committed by Tao Huang
parent 733b63c3b1
commit 995a5e0ef5
1 changed files with 1 additions and 1 deletions
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2
drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
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@@ -480,7 +480,7 @@ static int rk3528_combphy_cfg(struct rockchip_combphy_priv *priv)
/* Enable adaptive CTLE for USB3.0 Rx */
val = readl(priv->mmio + 0x200);
val &= ~GENMASK(17, 17);
val |= 0x01;
val |= 0x01 << 17;
writel(val, priv->mmio + 0x200);
param_write(priv->phy_grf, &cfg->pipe_txcomp_sel, false);