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sm1: emmc run hs200 busmode [1/1]
PD#SWPL-5404 Problem: emmc report data crc error in hs200 busmode Solution: set hs200 co_phase to 2 and did not reset the hs200 co_phase and tx_phase when adjust tuning is find the error point in sm1 Verify: verify pass on sm1_s905d3_ac200 Change-Id: I56aa8eb666fb55641db75878a3488f66c721bd6d Signed-off-by: ruixuan.li <ruixuan.li@amlogic.com>
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@@ -3641,6 +3641,32 @@ static struct meson_mmc_data mmc_data_tl1 = {
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.sdmmc.sdr104.core_phase = 2,
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};
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static struct meson_mmc_data mmc_data_sm1 = {
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.chip_type = MMC_CHIP_SM1,
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.port_a_base = 0xffe03000,
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.port_b_base = 0xffe05000,
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.port_c_base = 0xffe07000,
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.pinmux_base = 0xff634400,
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.clksrc_base = 0xff63c000,
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.ds_pin_poll = 0x3a,
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.ds_pin_poll_en = 0x48,
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.ds_pin_poll_bit = 13,
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.sdmmc.init.core_phase = 3,
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.sdmmc.init.tx_phase = 0,
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.sdmmc.init.rx_phase = 0,
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.sdmmc.calc.core_phase = 0,
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.sdmmc.calc.tx_phase = 2,
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.sdmmc.hs.core_phase = 3,
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.sdmmc.ddr.core_phase = 2,
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.sdmmc.ddr.tx_phase = 0,
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.sdmmc.hs2.core_phase = 2,
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.sdmmc.hs2.tx_phase = 0,
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.sdmmc.hs4.tx_delay = 0,
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.sdmmc.sd_hs.core_phase = 3,
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.sdmmc.sdr104.core_phase = 2,
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.sdmmc.sdr104.tx_phase = 0,
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};
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static const struct of_device_id meson_mmc_of_match[] = {
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{
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.compatible = "amlogic, meson-mmc-gxbb",
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@@ -1192,8 +1192,10 @@ tunning:
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nmatch = aml_sd_emmc_tuning_transfer(mmc, opcode,
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blk_pattern, host->blk_test, blksz);
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if (nmatch != TUNING_NUM_PER_POINT) {
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clkc->core_phase = para->hs2.tx_phase;
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clkc->tx_phase = para->hs2.core_phase;
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if (host->data->chip_type != MMC_CHIP_SM1) {
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clkc->core_phase = para->hs2.tx_phase;
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clkc->tx_phase = para->hs2.core_phase;
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}
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writel(vclk, host->base + SD_EMMC_CLOCK_V3);
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pr_info("%s:try clock:0x%x>>>rx_tuning[%d] = %d\n",
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mmc_hostname(host->mmc),
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