clk: rockchip: add a clock-type for muxes based in the pmugrf

Rockchip socs often have some tiny number of muxes not controlled from
the core clock controller but through bits set in the pmugrf.
Use MUXPMUGRF() to cover this special clock-type.

Change-Id: Iac962a27a3c88ce188d03c416cb4b3b45a462c0a
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
This commit is contained in:
Elaine Zhang
2019-03-07 14:46:17 +08:00
committed by Tao Huang
parent a651a11d16
commit 9c9278d549
2 changed files with 26 additions and 0 deletions

View File

@@ -429,6 +429,8 @@ struct rockchip_clk_provider * __init rockchip_clk_init(struct device_node *np,
ctx->grf = syscon_regmap_lookup_by_phandle(ctx->cru_node,
"rockchip,grf");
ctx->pmugrf = syscon_regmap_lookup_by_phandle(ctx->cru_node,
"rockchip,pmugrf");
return ctx;
@@ -504,6 +506,13 @@ void __init rockchip_clk_register_branches(
list->mux_shift, list->mux_width,
list->mux_flags);
break;
case branch_muxpmugrf:
clk = rockchip_clk_register_muxgrf(list->name,
list->parent_names, list->num_parents,
flags, ctx->pmugrf, list->muxdiv_offset,
list->mux_shift, list->mux_width,
list->mux_flags);
break;
case branch_divider:
if (list->div_table)
clk = clk_register_divider_table(NULL,

View File

@@ -272,6 +272,7 @@ struct rockchip_clk_provider {
struct clk_onecell_data clk_data;
struct device_node *cru_node;
struct regmap *grf;
struct regmap *pmugrf;
spinlock_t lock;
};
@@ -426,6 +427,7 @@ enum rockchip_clk_branch_type {
branch_composite,
branch_mux,
branch_muxgrf,
branch_muxpmugrf,
branch_divider,
branch_fraction_divider,
branch_gate,
@@ -698,6 +700,21 @@ struct rockchip_clk_branch {
.gate_offset = -1, \
}
#define MUXPMUGRF(_id, cname, pnames, f, o, s, w, mf) \
{ \
.id = _id, \
.branch_type = branch_muxpmugrf, \
.name = cname, \
.parent_names = pnames, \
.num_parents = ARRAY_SIZE(pnames), \
.flags = f, \
.muxdiv_offset = o, \
.mux_shift = s, \
.mux_width = w, \
.mux_flags = mf, \
.gate_offset = -1, \
}
#define DIV(_id, cname, pname, f, o, s, w, df) \
{ \
.id = _id, \