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video: rockchip: rga3: add disable-mode-ctrl register definition

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Change-Id: I9dd5b8d7a6f1e979786ec5ca32509cd48dc4b5fa
Signed-off-by: Yu Qiaowei <cerf.yu@rock-chips.com>
This commit is contained in:
Yu Qiaowei
2023-12-21 16:57:37 +08:00
committed by Tao Huang
parent 78365dd0d6
commit 9d3a698344
1 changed files with 9 additions and 0 deletions
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9
drivers/video/rockchip/rga3/include/rga2_reg_info.h
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@@ -206,6 +206,10 @@
#define m_RGA2_MODE_CTRL_SW_TILE4x4_IN_EN (0x1 << 12)
#define m_RGA2_MODE_CTRL_SW_TILE4x4_OUT_EN (0x1 << 13)
#define m_RGA2_MODE_CTRL_SW_FBC_IN_EN (0x1 << 16)
#define m_RGA2_MODE_CTRL_SW_FBC_BSP_DIS (0x1 << 18)
#define m_RGA2_MODE_CTRL_SW_TABLE_PRE_FETCH_DIS (0x1 << 19)
#define m_RGA2_MODE_CTRL_SW_AXI_WR128_DIS (0x1 << 20)
#define m_RGA2_MODE_CTRL_SW_HSP_LEFT_COPY_DIS (0x1 << 21)
#define s_RGA2_MODE_CTRL_SW_RENDER_MODE(x) ((x & 0x7) << 0)
#define s_RGA2_MODE_CTRL_SW_BITBLT_MODE(x) ((x & 0x1) << 3)
@@ -219,6 +223,11 @@
#define s_RGA2_MODE_CTRL_SW_TILE4x4_IN_EN(x) ((x & 0x1) << 12)
#define s_RGA2_MODE_CTRL_SW_TILE4x4_OUT_EN(x) ((x & 0x1) << 13)
#define s_RGA2_MODE_CTRL_SW_FBC_IN_EN(x) ((x & 0x1) << 16)
#define s_RGA2_MODE_CTRL_SW_FBC_BSP_DIS(x) ((x & 0x1) << 18)
#define s_RGA2_MODE_CTRL_SW_TABLE_PRE_FETCH_DIS(x) ((x & 0x1) << 19)
#define s_RGA2_MODE_CTRL_SW_AXI_WR128_DIS(x) ((x & 0x1) << 20)
#define s_RGA2_MODE_CTRL_SW_HSP_LEFT_COPY_DIS(x) ((x & 0x1) << 21)
/* RGA_SRC_INFO */
#define m_RGA2_SRC_INFO_SW_SRC_FMT (0xf << 0)
#define m_RGA2_SRC_INFO_SW_FBCIN_MODE (0x3 << 0) // repeat