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clk: rockchip: rv1126: Add support for otp

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Change-Id: I5ec48815522decfba8cbd9be7ec015019744a63e
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
This commit is contained in:
Finley Xiao
2020-02-28 15:02:31 +08:00
committed by Tao Huang
parent a39f5d2a43
commit 9dd115ef8c
2 changed files with 6 additions and 1 deletions
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3
drivers/clk/rockchip/clk-rv1126.c
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@@ -681,6 +681,9 @@ static struct rockchip_clk_branch rv1126_clk_branches[] __initdata = {
COMPOSITE(CLK_CAN, "clk_can", mux_gpll_xin24m_p, 0,
RV1126_CLKSEL_CON(25), 1, 1, MFLAGS, 0, 7, DFLAGS,
RV1126_CLKGATE_CON(7), 9, GFLAGS),
/* pclk_otp and clk_otp are controlled by sgrf_clkgat_con. */
SGRF_GATE(CLK_OTP, "clk_otp", "xin24m"),
SGRF_GATE(PCLK_OTP, "pclk_otp", "pclk_pdbus"),
GATE(PCLK_NPU_TSADC, "pclk_npu_tsadc", "pclk_pdbus", 0,
RV1126_CLKGATE_CON(24), 3, GFLAGS),

4
include/dt-bindings/clock/rv1126-cru.h
View File

@@ -211,6 +211,7 @@
#define CLK_CORE_NPUPVTM 145
#define CLK_NPUPVTM 146
#define SCLK_DDRCLK 147
#define CLK_OTP 148
/* dclk */
#define DCLK_DECOM 150
@@ -351,8 +352,9 @@
#define PCLK_CSIPHY1 291
#define PCLK_USBPHY_HOST 292
#define PCLK_USBPHY_OTG 293
#define PCLK_OTP 294
#define CLK_NR_CLKS (PCLK_USBPHY_OTG + 1)
#define CLK_NR_CLKS (PCLK_OTP + 1)
/* pmu soft-reset indices */