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ASoC: rk_codec_digital: fix register definition error

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Fixes: 5d33c809c3 ("ASoC: codecs: Add support for rockchip codec digital interface")
Signed-off-by: Jason Zhu <jason.zhu@rock-chips.com>
Change-Id: I867538d4aef82120b9cefa2cf833ccfe43f11596
This commit is contained in:
Jason Zhu
2023-03-01 15:44:54 +08:00
committed by Tao Huang
parent dba7790c26
commit 9ec9e12850
2 changed files with 11 additions and 6 deletions
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8
sound/soc/codecs/rk_codec_digital.c
View File

@@ -407,13 +407,13 @@ static int rk_codec_digital_set_clk_sync(struct rk_codec_digital_priv *rcd,
ACDCDIG_DACSCLKRXINT_DIV_SCKRXDIV(div_bclk));
regmap_update_bits(rcd->regmap, I2S_CKR0,
ACDCDIG_I2S_CKR0_RSD_MASK,
ACDCDIG_I2S_CKR0_RSD(64));
ACDCDIG_I2S_CKR0_RSD_64);
regmap_update_bits(rcd->regmap, ADCSCLKTXINT_DIV,
ACDCDIG_ADCSCLKTXINT_DIV_SCKTXDIV_MASK,
ACDCDIG_ADCSCLKTXINT_DIV_SCKTXDIV(div_bclk));
regmap_update_bits(rcd->regmap, I2S_CKR0,
ACDCDIG_I2S_CKR0_TSD_MASK,
ACDCDIG_I2S_CKR0_TSD(64));
ACDCDIG_I2S_CKR0_TSD_64);
return 0;
}
@@ -450,7 +450,7 @@ static int rk_codec_digital_set_clk(struct rk_codec_digital_priv *rcd,
ACDCDIG_DACSCLKRXINT_DIV_SCKRXDIV(div_bclk));
regmap_update_bits(rcd->regmap, I2S_CKR0,
ACDCDIG_I2S_CKR0_RSD_MASK,
ACDCDIG_I2S_CKR0_RSD(64));
ACDCDIG_I2S_CKR0_RSD_64);
} else {
clk_set_rate(rcd->clk_adc, mclk);
@@ -464,7 +464,7 @@ static int rk_codec_digital_set_clk(struct rk_codec_digital_priv *rcd,
ACDCDIG_ADCSCLKTXINT_DIV_SCKTXDIV(div_bclk));
regmap_update_bits(rcd->regmap, I2S_CKR0,
ACDCDIG_I2S_CKR0_TSD_MASK,
ACDCDIG_I2S_CKR0_TSD(64));
ACDCDIG_I2S_CKR0_TSD_64);
}
return 0;

9
sound/soc/codecs/rk_codec_digital.h
View File

@@ -288,9 +288,14 @@
#define ACDCDIG_I2S_RXCR1_RCSR_2CH (0x0 << 6)
/* I2S_CKR0 */
#define ACDCDIG_I2S_CKR0_TSD_MASK GENMASK(1, 0)
#define ACDCDIG_I2S_CKR0_TSD(x) ((x) << 0)
#define ACDCDIG_I2S_CKR0_TSD_64 (0 << 0)
#define ACDCDIG_I2S_CKR0_TSD_128 (1 << 0)
#define ACDCDIG_I2S_CKR0_TSD_256 (2 << 0)
#define ACDCDIG_I2S_CKR0_RSD_MASK GENMASK(3, 2)
#define ACDCDIG_I2S_CKR0_RSD(x) ((x) << 2)
#define ACDCDIG_I2S_CKR0_RSD_64 (0 << 2)
#define ACDCDIG_I2S_CKR0_RSD_128 (1 << 2)
#define ACDCDIG_I2S_CKR0_RSD_256 (2 << 2)
/* I2S_CKR1 */
#define ACDCDIG_I2S_CKR1_TLP_MASK BIT(0)
#define ACDCDIG_I2S_CKR1_TLP_INVERTED BIT(0)