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media: rockchip: vicap fixes pclk polarity for rv1106

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Fixes: 74aca7167d ("media: rockchip: rv1106 vicap support dvp")
Signed-off-by: Zefa Chen <zefa.chen@rock-chips.com>
Change-Id: I521d0f56061486f7db4ebe283382aa69c4f2d5e3
This commit is contained in:
Zefa Chen
2023-03-01 15:41:54 +08:00
committed by Tao Huang
parent 309faf4a9c
commit dba7790c26
1 changed files with 4 additions and 4 deletions
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8
drivers/media/platform/rockchip/cif/regs.h
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@@ -1047,10 +1047,10 @@ enum cif_reg_index {
#define RV1106_CIF_GRF_VENC_WRAPPER (0x10008)
#define RV1106_CIF_PCLK_SINGLE_EDGE (0x00040000)
#define RV1106_CIF_PCLK_DUAL_EDGE (0x00040004)
#define RV1106_CIF_PCLK_EDGE_RISING_M0 (0x00020000)
#define RV1106_CIF_PCLK_EDGE_FALLING_M0 (0x00020002)
#define RV1106_CIF_PCLK_EDGE_RISING_M1 (0x00010000)
#define RV1106_CIF_PCLK_EDGE_FALLING_M1 (0x00010001)
#define RV1106_CIF_PCLK_EDGE_RISING_M0 (0x00020002)
#define RV1106_CIF_PCLK_EDGE_FALLING_M0 (0x00020000)
#define RV1106_CIF_PCLK_EDGE_RISING_M1 (0x00010001)
#define RV1106_CIF_PCLK_EDGE_FALLING_M1 (0x00010000)
#define RV1106_CIF_GRF_SEL_M0 (0x00010000)
#define RV1106_CIF_GRF_SEL_M1 (0x00010001)