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ethernet: stmmac: rockchip: Fix the correct clock for mdc divider

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The MDC clock is divider from APB Clock for rockchip's socs, if it
was from mac_clk, the mdc clk range might not be between the frequency
range 1.0 MHz - 2.5 MHz.

Change-Id: I4e4fcb1be239a8d78a39fc1f4e2af5bb87258798
Signed-off-by: David Wu <david.wu@rock-chips.com>
This commit is contained in:
David Wu
2017-04-28 17:33:24 +08:00
committed by Tao Huang
parent 702c177bec
commit a19f9979e4
2 changed files with 2 additions and 2 deletions
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2
drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
View File

@@ -206,7 +206,7 @@ static void stmmac_clk_csr_set(struct stmmac_priv *priv)
{
u32 clk_rate;
clk_rate = clk_get_rate(priv->plat->stmmac_clk);
clk_rate = clk_get_rate(priv->plat->pclk);
/* Platform provided default clk_csr would be assumed valid
* for all other cases except for the below mentioned ones.

2
drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c
View File

@@ -576,7 +576,7 @@ stmmac_probe_config_dt(struct platform_device *pdev, const char **mac)
clk_prepare_enable(plat->stmmac_clk);
}
plat->pclk = devm_clk_get(&pdev->dev, "pclk");
plat->pclk = devm_clk_get(&pdev->dev, "pclk_mac");
if (IS_ERR(plat->pclk)) {
if (PTR_ERR(plat->pclk) == -EPROBE_DEFER)
goto error_pclk_get;