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Merge commit 'f131a6b432efe9c3fdc78370e569af4e3eb4cf64'

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* commit 'f131a6b432efe9c3fdc78370e569af4e3eb4cf64':
  drm/rockchip: vop2: move frc v2 dither config to crtc aotmic enable
  drm/bridge: synopsys: dw-hdmi-qp: Don't read scdc regs with hdmi1.4 sink
  gpio: rockchip: don't use debounce config function
  ASoC: rk817: Resolve POP noise when starting recording during playback

Change-Id: I30e284df6eba56ffbccf2d8b6669f0c011c3dc5b
This commit is contained in:
Tao Huang
2024-09-30 17:21:50 +08:00
parent c40badb07a f131a6b432
commit a417d17d5d
7 changed files with 38 additions and 24 deletions
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8
drivers/gpio/gpio-rockchip.c
View File

@@ -292,11 +292,15 @@ static int rockchip_gpio_set_config(struct gpio_chip *gc, unsigned int offset,
unsigned long config)
{
enum pin_config_param param = pinconf_to_config_param(config);
unsigned int debounce = pinconf_to_config_argument(config);
switch (param) {
case PIN_CONFIG_INPUT_DEBOUNCE:
return rockchip_gpio_set_debounce(gc, offset, debounce);
rockchip_gpio_set_debounce(gc, offset, 0);
/*
* Since Rockchip's GPIO hardware debounce function does not
* support configuring individual pins, it will not be used.
*/
return -ENOTSUPP;
default:
return -ENOTSUPP;
}

4
drivers/gpu/drm/bridge/synopsys/dw-hdmi-qp.c
View File

@@ -3179,7 +3179,9 @@ static int dw_hdmi_connector_atomic_check(struct drm_connector *connector,
extcon_set_state_sync(hdmi->extcon, EXTCON_DISP_HDMI, true);
}
drm_scdc_readb(hdmi->ddc, SCDC_TMDS_CONFIG, &val);
val = 0;
if (dw_hdmi_support_scdc(hdmi, &connector->display_info))
drm_scdc_readb(hdmi->ddc, SCDC_TMDS_CONFIG, &val);
/* if plug out before hdmi bind, reset hdmi */
if (vmode->mtmdsclock >= 340000000 && vmode->mpixelclock <= 600000000 &&
!(val & SCDC_TMDS_BIT_CLOCK_RATIO_BY_40) && !hdmi->force_kernel_output)

3
drivers/gpu/drm/rockchip/rockchip_drm_vop.h
View File

@@ -898,6 +898,9 @@ struct vop2_video_port_regs {
struct vop_reg dither_down_mode;
struct vop_reg dither_down_en;
struct vop_reg pre_dither_down_en;
struct vop_reg dither_frc_0;
struct vop_reg dither_frc_1;
struct vop_reg dither_frc_2;
struct vop_reg dither_up_en;
struct vop_reg bg_dly;

14
drivers/gpu/drm/rockchip/rockchip_drm_vop2.c
View File

@@ -4383,14 +4383,6 @@ static void vop2_initial(struct drm_crtc *crtc)
/* Default use rkiommu 1.0 for axi0 */
VOP_CTRL_SET(vop2, rkmmu_v2_en, 0);
/* Init frc2.0 config */
vop2_writel(vop2, 0xca0, 0xc8);
vop2_writel(vop2, 0xca4, 0x01000100);
vop2_writel(vop2, 0xca8, 0x03ff0100);
vop2_writel(vop2, 0xda0, 0xc8);
vop2_writel(vop2, 0xda4, 0x01000100);
vop2_writel(vop2, 0xda8, 0x03ff0100);
if (vop2->merge_irq == true)
VOP_CTRL_SET(vop2, vp_intr_merge_en, 1);
VOP_CTRL_SET(vop2, lut_use_axi1, 0);
@@ -8103,9 +8095,9 @@ static void vop2_dither_setup(struct rockchip_crtc_state *vcstate, struct drm_cr
pre_dither_down_en = false;
if (vp_data->feature & VOP_FEATURE_POST_FRC_V2 && pre_dither_down_en) {
vop2_writel(vop2, RK3576_VP0_POST_DITHER_FRC_0, 0x00000000);
vop2_writel(vop2, RK3576_VP0_POST_DITHER_FRC_1, 0x01000100);
vop2_writel(vop2, RK3576_VP0_POST_DITHER_FRC_2, 0x04030100);
VOP_MODULE_SET(vop2, vp, dither_frc_0, 0x00000000);
VOP_MODULE_SET(vop2, vp, dither_frc_1, 0x01000100);
VOP_MODULE_SET(vop2, vp, dither_frc_2, 0x04030100);
VOP_MODULE_SET(vop2, vp, pre_dither_down_en, 0);
VOP_MODULE_SET(vop2, vp, dither_down_en, 1);/* enable frc2.0 do 10->8 */

6
drivers/gpu/drm/rockchip/rockchip_vop2_reg.c
View File

@@ -1487,6 +1487,9 @@ static const struct vop2_video_port_regs rk3576_vop_vp0_regs = {
.post_dsp_out_r2y = VOP_REG(RK3568_VP0_DSP_CTRL, 0x1, 15),
.pre_dither_down_en = VOP_REG(RK3568_VP0_DSP_CTRL, 0x1, 16),
.dither_down_en = VOP_REG(RK3568_VP0_DSP_CTRL, 0x1, 17),
.dither_frc_0 = VOP_REG(RK3576_VP0_POST_DITHER_FRC_0, 0xffffffff, 0),
.dither_frc_1 = VOP_REG(RK3576_VP0_POST_DITHER_FRC_1, 0xffffffff, 0),
.dither_frc_2 = VOP_REG(RK3576_VP0_POST_DITHER_FRC_2, 0xffffffff, 0),
.dither_down_sel = VOP_REG(RK3568_VP0_DSP_CTRL, 0x3, 18),
.dither_down_mode = VOP_REG(RK3568_VP0_DSP_CTRL, 0x1, 20),
.gamma_update_en = VOP_REG(RK3568_VP0_DSP_CTRL, 0x1, 22),
@@ -1600,6 +1603,9 @@ static const struct vop2_video_port_regs rk3576_vop_vp1_regs = {
.post_dsp_out_r2y = VOP_REG(RK3568_VP1_DSP_CTRL, 0x1, 15),
.pre_dither_down_en = VOP_REG(RK3568_VP1_DSP_CTRL, 0x1, 16),
.dither_down_en = VOP_REG(RK3568_VP1_DSP_CTRL, 0x1, 17),
.dither_frc_0 = VOP_REG(RK3576_VP1_POST_DITHER_FRC_0, 0xffffffff, 0),
.dither_frc_1 = VOP_REG(RK3576_VP1_POST_DITHER_FRC_1, 0xffffffff, 0),
.dither_frc_2 = VOP_REG(RK3576_VP1_POST_DITHER_FRC_2, 0xffffffff, 0),
.dither_down_sel = VOP_REG(RK3568_VP1_DSP_CTRL, 0x3, 18),
.dither_down_mode = VOP_REG(RK3568_VP1_DSP_CTRL, 0x1, 20),
.gamma_update_en = VOP_REG(RK3568_VP1_DSP_CTRL, 0x1, 22),

3
drivers/gpu/drm/rockchip/rockchip_vop_reg.h
View File

@@ -1201,6 +1201,9 @@
#define RK3568_VP1_BCSH_BCS 0xD64
#define RK3568_VP1_BCSH_H 0xD68
#define RK3568_VP1_BCSH_COLOR_BAR 0xD6C
#define RK3576_VP1_POST_DITHER_FRC_0 0xDA0
#define RK3576_VP1_POST_DITHER_FRC_1 0xDA4
#define RK3576_VP1_POST_DITHER_FRC_2 0xDA8
#define RK3562_VP1_MCU_CTRL 0xDF8
#define RK3562_VP1_MCU_RW_BYPASS_PORT 0xDFC

24
sound/soc/codecs/rk817_codec.c
View File

@@ -542,6 +542,7 @@ static int rk817_codec_power_up(struct snd_soc_component *component, int type)
static int rk817_codec_power_down(struct snd_soc_component *component, int type)
{
struct rk817_codec_priv *rk817 = snd_soc_component_get_drvdata(component);
int i;
DBG("%s : power down %s %s %s\n", __func__,
@@ -592,6 +593,7 @@ static int rk817_codec_power_down(struct snd_soc_component *component, int type)
snd_soc_component_write(component, RK817_CODEC_DTOP_DIGEN_CLKE, 0x00);
snd_soc_component_write(component, RK817_CODEC_APLL_CFG5, 0x01);
snd_soc_component_write(component, RK817_CODEC_AREF_RTCFG1, 0x06);
rk817->rate = 0;
}
return 0;
@@ -1041,19 +1043,12 @@ static int rk817_set_dai_sysclk(struct snd_soc_dai *codec_dai,
{
struct snd_soc_component *component = codec_dai->component;
struct rk817_codec_priv *rk817 = snd_soc_component_get_drvdata(component);
unsigned int ret = 0;
ret = clk_set_rate(rk817->mclk, freq);
if (ret) {
dev_warn(component->dev, "%s %d clk_set_rate %d failed\n",
__func__, __LINE__, freq);
return ret;
}
rk817->stereo_sysclk = freq;
DBG("%s : MCLK = %dHz\n", __func__, rk817->stereo_sysclk);
return ret;
return 0;
}
static int rk817_set_dai_fmt(struct snd_soc_dai *codec_dai,
@@ -1090,8 +1085,9 @@ static int rk817_hw_params(struct snd_pcm_substream *substream,
unsigned int rate = params_rate(params);
unsigned char apll_cfg3_val;
unsigned char dtop_digen_sr_lmt0;
unsigned int ret = 0;
DBG("%s : sample rate = %dHz\n", __func__, rate);
DBG("%s : pre sample rate = %d, cur sample rate = %dHz\n", __func__, rk817->rate, rate);
if (rk817->chip_ver <= 0x4) {
DBG("%s: 0x4 and previous versions\n", __func__);
@@ -1132,7 +1128,12 @@ static int rk817_hw_params(struct snd_pcm_substream *substream,
* is before playback/capture_path_put, therefore, we need to configure
* APLL_CFG3/DTOP_DIGEN_CLKE/DDAC_SR_LMT0 for different sample rates.
*/
if (!((substream->stream == SNDRV_PCM_STREAM_CAPTURE) && rk817->pdmdata_out_enable)) {
if ((rk817->rate != rate) &&
!((substream->stream == SNDRV_PCM_STREAM_CAPTURE) && rk817->pdmdata_out_enable)) {
ret = clk_set_rate(rk817->mclk, rk817->stereo_sysclk);
if (ret)
dev_warn(component->dev, "%s %d clk_set_rate %d failed\n",
__func__, __LINE__, rk817->stereo_sysclk);
snd_soc_component_write(component, RK817_CODEC_APLL_CFG3, apll_cfg3_val);
snd_soc_component_update_bits(component, RK817_CODEC_DDAC_SR_LMT0,
DACSRT_MASK, dtop_digen_sr_lmt0);
@@ -1142,6 +1143,8 @@ static int rk817_hw_params(struct snd_pcm_substream *substream,
rk817_restart_adc_digital_clk_and_apll(component);
}
rk817->rate = rate;
switch (params_format(params)) {
case SNDRV_PCM_FORMAT_S16_LE:
snd_soc_component_write(component, RK817_CODEC_DI2S_RXCR2,
@@ -1378,6 +1381,7 @@ static int rk817_probe(struct snd_soc_component *component)
rk817->component = component;
rk817->playback_path = OFF;
rk817->capture_path = MIC_OFF;
rk817->rate = 0;
chip_name = snd_soc_component_read(component, RK817_PMIC_CHIP_NAME);
chip_ver = snd_soc_component_read(component, RK817_PMIC_CHIP_VER);