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Revert "clk: rockchip: Set parent rate for DCLK_VOP clock on RK3228"

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This reverts commit a3f77b5d16.

RK3228 Only GPLL and CPLL, GPLL is a common clock, does not allow dclk_vop
to change its frequency, CPLL is used by GMAC, if dclk_vop use
CLK_SET_RATE_PARENT and CLK_SET_RATE_NO_REPARENT flags will
affect the GMAC function.

Change-Id: I2c959a19f115b34720364586c374fc6e01fc8eb4
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
This commit is contained in:
Elaine Zhang
2025-01-20 17:21:58 +08:00
committed by Tao Huang
parent 4388d47efb
commit a56129cb0c
1 changed files with 1 additions and 1 deletions
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2
drivers/clk/rockchip/clk-rk3228.c
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@@ -410,7 +410,7 @@ static struct rockchip_clk_branch rk3228_clk_branches[] __initdata = {
RK2928_CLKSEL_CON(29), 0, 3, DFLAGS),
DIV(0, "sclk_vop_pre", "sclk_vop_src", 0,
RK2928_CLKSEL_CON(27), 8, 8, DFLAGS),
MUX(DCLK_VOP, "dclk_vop", mux_dclk_vop_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
MUX(DCLK_VOP, "dclk_vop", mux_dclk_vop_p, 0,
RK2928_CLKSEL_CON(27), 1, 1, MFLAGS),
FACTOR(0, "xin12m", "xin24m", 0, 1, 2),