shinys000114/linux
1
0
Fork 0
mirror of https://github.com/hardkernel/linux.git synced 2026-06-08 03:40:35 +09:00
Code Issues Packages Projects Releases Wiki Activity

clk: rockchip: rk3228: add clk_ddrc for devfreq of ddr

Browse Source 
Change-Id: I3771e2ef68ab3fa8ad1b7d61a84c7181c693c60f
Signed-off-by: Liang Chen <cl@rock-chips.com>
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
This commit is contained in:
Liang Chen
2018-02-05 15:38:17 +08:00
committed by Tao Huang
parent 47742edbbd
commit a561d683ac
2 changed files with 6 additions and 8 deletions
Download Patch File Download Diff File Expand all files Collapse all files

13
drivers/clk/rockchip/clk-rk3228.c
View File

@@ -226,15 +226,12 @@ static struct rockchip_clk_branch rk3228_clk_branches[] __initdata = {
RK2928_CLKSEL_CON(4), 8, 5, DFLAGS),
/* PD_DDR */
COMPOSITE(0, "clk_ddrphy_src", mux_ddrphy_p, CLK_IGNORE_UNUSED,
RK2928_CLKSEL_CON(26), 8, 2, MFLAGS, 0, 2, DFLAGS | CLK_DIVIDER_POWER_OF_TWO,
RK2928_CLKGATE_CON(0), 2, GFLAGS),
GATE(0, "ddrphy4x", "clk_ddrphy_src", CLK_IGNORE_UNUSED,
COMPOSITE_DDRCLK(SCLK_DDRC, "clk_ddrc", mux_ddrphy_p, 0,
RK2928_CLKSEL_CON(26), 8, 2, 0, 2,
ROCKCHIP_DDRCLK_SIP_V2),
FACTOR(0, "clk_ddrphy", "clk_ddrc", 0, 1, 4),
GATE(0, "ddrphy4x", "clk_ddrc", CLK_IGNORE_UNUSED,
RK2928_CLKGATE_CON(7), 1, GFLAGS),
FACTOR_GATE(0, "ddrc", "clk_ddrphy_src", CLK_IGNORE_UNUSED, 1, 4,
RK2928_CLKGATE_CON(8), 5, GFLAGS),
FACTOR_GATE(0, "ddrphy", "clk_ddrphy_src", CLK_IGNORE_UNUSED, 1, 4,
RK2928_CLKGATE_CON(7), 0, GFLAGS),
/* PD_CORE */
GATE(0, "apll_core", "apll", CLK_IGNORE_UNUSED,

1
include/dt-bindings/clock/rk3228-cru.h
View File

@@ -73,6 +73,7 @@
#define SCLK_WIFI 141
#define SCLK_OTGPHY0 142
#define SCLK_OTGPHY1 143
#define SCLK_DDRC 144
/* dclk gates */
#define DCLK_VOP 190