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Revert "clk: rockchip: Modify uart frac divider rule"

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This reverts commit aa34d0fe71.
This rule does not cover the parent priority selection problem.

Change-Id: Id75d46548e28da378420f614b45a6b71c6601843
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
This commit is contained in:
Elaine Zhang
2019-08-23 15:59:43 +08:00
parent abfc038343
commit a5ba41ceff
1 changed files with 0 additions and 14 deletions
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14
drivers/clk/rockchip/clk.c
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@@ -195,19 +195,6 @@ static void rockchip_fractional_approximation(struct clk_hw *hw,
u32 div;
p_rate = clk_hw_get_rate(clk_hw_get_parent(hw));
if (strstr(clk_hw_get_name(hw), "uart")) {
if (rate <= 24000000) {
*parent_rate = 24000000;
} else {
if (fd->max_prate)
*parent_rate = fd->max_prate;
else
*parent_rate = 480000000;
}
goto frac_ration;
}
if (((rate * 20 > p_rate) && (p_rate % rate != 0)) ||
(fd->max_prate && fd->max_prate < p_rate)) {
p_parent = clk_hw_get_parent(clk_hw_get_parent(hw));
@@ -232,7 +219,6 @@ static void rockchip_fractional_approximation(struct clk_hw *hw,
}
}
frac_ration:
/*
* Get rate closer to *parent_rate to guarantee there is no overflow
* for m and n. In the result it will be the nearest rate left shifted