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phy: rockchip-naneng-combo: Add ssc support for pcie

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Best parameter: 24M T0_1 650mV.

Should co-work with change like below:

&combphy0_ps {
+	rockchip,enable-ssc;
+       assigned-clock-rates = <24000000>;
        status = "okay";
};

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Change-Id: I863b8d1758431c0037332e7da1b2c64cd7113573
This commit is contained in:
Kever Yang
2022-09-07 11:26:51 +08:00
committed by Tao Huang
parent 48401c5ee2
commit a648efab5e
1 changed files with 26 additions and 0 deletions
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26
drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
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@@ -664,6 +664,12 @@ static int rk3588_combphy_cfg(struct rockchip_combphy_priv *priv)
switch (priv->mode) {
case PHY_TYPE_PCIE:
/* Set SSC downward spread spectrum */
val = readl(priv->mmio + (0x1f << 2));
val &= ~GENMASK(5, 4);
val |= 0x01 << 4;
writel(val, priv->mmio + 0x7c);
param_write(priv->phy_grf, &cfg->con0_for_pcie, true);
param_write(priv->phy_grf, &cfg->con1_for_pcie, true);
param_write(priv->phy_grf, &cfg->con2_for_pcie, true);
@@ -841,6 +847,26 @@ static int rk3588_combphy_cfg(struct rockchip_combphy_priv *priv)
}
}
if (device_property_read_bool(priv->dev, "rockchip,enable-ssc")) {
val = readl(priv->mmio + (0x7 << 2));
val |= BIT(4);
writel(val, priv->mmio + (0x7 << 2));
if (priv->mode == PHY_TYPE_PCIE && rate == 24000000) {
/* Xin24M T0_1 650mV */
writel(0x00, priv->mmio + (0x10 << 2));
writel(0x32, priv->mmio + (0x11 << 2));
writel(0x00, priv->mmio + (0x1b << 2));
writel(0x90, priv->mmio + (0x0a << 2));
writel(0x02, priv->mmio + (0x0b << 2));
writel(0x08, priv->mmio + (0x0c << 2));
writel(0x57, priv->mmio + (0x0d << 2));
writel(0x40, priv->mmio + (0x0e << 2));
writel(0x5f, priv->mmio + (0x0f << 2));
writel(0x10, priv->mmio + (0x20 << 2));
}
}
return 0;
}