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phy: rockchip: naneng-combphy: Configuring grf with clk enabled

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Change-Id: Ie6c2e5dcd9936ff8e65783faee72ef55a8dce4d2
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
This commit is contained in:
Jon Lin
2025-03-05 16:29:54 +08:00
committed by Tao Huang
parent cc9141e700
commit a7ee710147
1 changed files with 9 additions and 0 deletions
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9
drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
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@@ -367,6 +367,13 @@ static int rockchip_combphy_parse_dt(struct device *dev,
return PTR_ERR(priv->phy_grf);
}
/* Configuring grf with cru enabled. */
ret = clk_bulk_prepare_enable(priv->num_clks, priv->clks);
if (ret) {
dev_err(priv->dev, "failed to enable clocks\n");
return ret;
}
if (device_property_present(dev, "rockchip,dis-u3otg0-port")) {
rockchip_combphy_param_write(priv->pipe_grf,
&cfg->u3otg0_port_en, false);
@@ -388,6 +395,8 @@ static int rockchip_combphy_parse_dt(struct device *dev,
regmap_write(priv->pipe_grf, vals[0],
(GENMASK(vals[2], vals[1]) << 16) | (vals[3] << vals[1]));
clk_bulk_disable_unprepare(priv->num_clks, priv->clks);
priv->apb_rst = devm_reset_control_get_optional(dev, "combphy-apb");
if (IS_ERR(priv->apb_rst)) {
ret = PTR_ERR(priv->apb_rst);