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drm/rockchip: dsi: add support dual-channel mode with independent PLL

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Display Pipeline:
                   ---> dsi0 --> dphy_tx0 --->
                  /                  |        \
                 /              dphy0_pll      \
      vp1/vp2 -->                               ---> panel
                 \              dphy1_pll      /
                  \                  |        /
                   ---> dsi1 --> dphy_tx1 --->


Change-Id: I9c975f29e2f40e04a1fac5c163aed0fa7cfb71e3
Signed-off-by: Guochun Huang <hero.huang@rock-chips.com>
This commit is contained in:
Guochun Huang
2020-11-09 20:44:39 +08:00
committed by Tao Huang
parent bf443367b9
commit a84097bf1d
1 changed files with 3 additions and 0 deletions
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3
drivers/gpu/drm/rockchip/dw-mipi-dsi.c
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@@ -1310,6 +1310,9 @@ static void dw_mipi_dsi_encoder_enable(struct drm_encoder *encoder)
else
dw_mipi_dsi_calc_pll_cfg(dsi, lane_rate);
if (dsi->slave && dsi->slave->dphy.phy)
dw_mipi_dsi_set_hs_clk(dsi->slave, lane_rate);
DRM_DEV_INFO(dsi->dev, "final DSI-Link bandwidth: %u x %d Mbps\n",
dsi->lane_mbps, dsi->slave ? dsi->lanes * 2 : dsi->lanes);